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參數(shù)資料
| 型號： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 25/48頁 |
| 文件大?。?/td> | 409K |
| 代理商： | INTEL486 GX |
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Embedded Ultra-Low Power Intel486 GX Processor
21
4.5.3.1 Multiple and Burst Cycle Bus Transfers
The embedded ULP Intel486 GX processor, like all
other Intel486 processors, requires more than one
data cycle to read or write data having bit widths
greater than 32. Examples of this data are cache
lines (128 bits) and instruction prefetches (128 bits).
In addition, the embedded ULP Intel486 GX
processor requires multiple data cycles to transfer
data having bit widths greater than 16. An example
is a doubleword operand (32 bits). Transferring mis-
aligned 16-bit words also requires multiple data
cycles.
If a multiple data cycle is a memory-read or I/O-read
data transfer, the processor could use burst cycles to
perform the transfer. The processor could also burst
misaligned 16-bit and 32-bit memory-write or I/O-
write data transfers.
In designing a memory and I/O port controller for the
embedded ULP Intel486 GX processor, knowledge
of the address sequence for burst cycles can be
used to provide high-speed data access (minimal
number of wait states). The following sections
describe this sequence.
4.5.3.2 Cacheable Cycles
The embedded ULP Intel486 GX processor uses
burst cycles to perform a cache line fill. Because of
its 16-bit external data bus, the processor bursts
eight data cycles to read a 128-bit (16-byte) cache
line from system memory. During the first cycle of
the cache line transfer, the external system must
ignore BE3#, BE2#, BE1#, and BE0# presented by
the processor and proceed as if A1, A0, and BHE#
were logic-low levels (0). This forces the memory
read to start from a data address having its least
significant hexadecimal digit 0, 4, 8, or C. The byte
enables presented by the processor for subsequent
cycles are decoded in the usual way by the external
system. The sequences of data addresses are
shown in Table 10. Like the rest of the Intel486
processor family, the initial value of A31-A4, M/IO#,
W/R#, and D/C# are presented by the processor
throughout the cache line fill. Also, the burst
sequence can be terminated by the processor at any
time by with an active BLAST# signal.
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