參數(shù)資料
型號(hào)： INTEL486 GX
廠商： Intel Corp.
英文描述： Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器)
中文描述： Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器）
文件頁數(shù)： 16/48頁
文件大小： 409K
代理商： INTEL486 GX
Embedded Ultra-Low Power Intel486 GX Processor
12
PAGE CACHEABILITY
PWT
PCD
O
O
Page Write-Through
and
Page Cache Disable
pins reflect the state of the page
attribute bits, PWT and PCD, in the page table entry, page directory entry or
control register 3 (CR3) when paging is enabled. When paging is disabled, the
embedded ULP Intel486 GX processor ignores the PCD and PWT bits and
assumes they are zero for the purpose of caching and driving PCD and PWT pins.
PWT and PCD have the same timing as the cycle definition pins (M/IO#, D/C#, and
W/R#). PWT and PCD are active HIGH and are not driven during bus hold. PCD is
masked by the cache disable bit (CD) in Control Register 0.
ADDRESS MASK
A20M#
I
Address Bit 20 Mask
pin, when asserted, causes the embedded ULP Intel486 GX
processor to mask physical address bit 20 (A20) before performing a lookup to the
internal cache or driving a memory cycle on the bus. A20M# emulates the address
wraparound at 1 Mbyte, which occurs on the 8086 processor. A20M# is active
LOW and should be asserted only when the embedded ULP Intel486 GX
processor is in real mode. This pin is asynchronous but should meet setup and
hold times t
and t
for recognition in any specific clock. For proper operation,
A20M# should be sampled HIGH at the falling edge of RESET.
TEST ACCESS PORT
TCK
I
Test Clock
, an input to the embedded ULP Intel486 GX processor, provides the
clocking function required by the JTAG Boundary scan feature. TCK is used to
clock state information (via TMS) and data (via TDI) into the component on the
rising edge of TCK. Data is clocked out of the component (via TDO) on the falling
edge of TCK. TCK is provided with an internal pull-up resistor.
Test Data Input
is the serial input used to shift JTAG instructions and data into the
processor. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and
SHIFT-DR TAP controller states. During all other Test Access Port (TAP) controller
states, TDI is a “don’t care.” TDI is provided with an internal pull-up resistor.
Test Data Output
is the serial output used to shift JTAG instructions and data out
of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR
and SHIFT-DR TAP controller states. At all other times TDO is driven to the high
impedance state.
Test Mode Select
is decoded by the JTAG TAP to select test logic operation. TMS
is sampled on the rising edge of TCK. To guarantee deterministic behavior of the
TAP controller, TMS is provided with an internal pull-up resistor.
TDI
I
TDO
O
TMS
I
RESERVED PINS
RESERVED#
I
Reserved
is reserved for future use. This pin MUST be connected to an external
pull-up resistor circuit. The recommended resistor value is 10 kOhms.
Table 4. Embedded ULP Intel486
GX Processor Pin Descriptions
(Sheet 6 of 6)
Symbol
Type
Name and Function
相關(guān)PDF資料
PDF描述
INTEL486 SX Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器)
INTEL82801 82801AB (ICH0) I/O Controller Hub
INTEL82802AB Firmware Hub (FWH)
INTELDX2 High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器)
INTELDX4 Embedded Write-Back Enhanced Processor(32位回復(fù)嵌入式增強(qiáng)型處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
INTEL740 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator
INTEL82801 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub
INTEL82802AB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Firmware Hub (FWH)
INTELLIGENT CHARGER + 4AA 制造商:Energizer 功能描述:Bulk
INTELLI-INCH-LR-STARTER K 制造商:ALL MOTION 功能描述:Intelli-Inch Stepper & Controller Starter Kit
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*