- 您現(xiàn)在的位置：買賣IC網 > PDF目錄377496 > INTEL486 GX (Intel Corp.) Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) PDF資料下載
參數(shù)資料
| 型號： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 23/48頁 |
| 文件大?。?/td> | 409K |
| 代理商： | INTEL486 GX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
19
Embedded Ultra-Low Power Intel486 GX Processor
4.5
Bus Interface and Operation
4.5.1
16-Bit Data Bus
The bi-directional lines, D15-D0, form the data bus
for the embedded ULP Intel486 GX processor. D7-
D0 define the least-significant byte and D15-D8 the
most-significant byte. Data transfers are possible
only to 16-bit devices. Bus-sizing for 8-bit devices
(BS8# signal pin) is not supported by the processor.
In some cases, external circuitry is needed for the
processor to interface with 8-bit devices. An example
of when external circuitry is not needed is an 8-bit
I/O port that is mapped to a byte address. Here only
part of the 16-bit data word is meant for the device
and BS8# is not needed.
D15-D0 are active HIGH. For reads, D15-D0 must
meet the setup and hold times, t
and t
. D15-D0
are not driven during read cycles and bus hold.
4.5.2
Parity
Parity operation is the same as it is for the rest of the
Intel486 processor family, with these exceptions:
DP0 and DP1 are the data parity pins for the
processor. There is one parity signal for each byte
of the external data bus. Input signals on DP0 and
DP1 must meet the setup and hold times, t
and
t
. In systems not using parity, DP0 and DP1
must be connected to VCCP through a pull-up
resistor.
The data parity pins have level-keeper circuits
which are described later.
4.5.3
Data Transfer Mechanism
Data transfers operate in a manner similar to data
transfers on the 32-bit data bus members of the
Intel486 processor family with the BS16# pin driven
active. For 32-bit data-bus family members, such 16-
bit data transfers involve all 32 bits of their external
data busses and all four parity bits. Since the
embedded ULP Intel486 GX processor has a 16-bit
external data bus, all data transfers occur on the low
order data bits, D0 through D15. Parity is generated
and checked on DP0 and DP1. Dynamic Data Bus
Sizing (BS16#, and BS8#) is not supported. All
address bits (A31-A2) and byte enables (BE0#,
BE1#, BE2#, and BE3#) are supported. Address bits
A1 and A0 can be generated from the byte-enable
signals in the same manner as the other Intel486
processors. Typically in 16-bit data bus designs, A1,
byte-low enable (BLE), and byte-high enable (BHE)
are needed and can be generated from the four
byte-enable signals. Figure 5 shows the logic that
can be used to generate A1, BHE#, and BLE#.
Figure 5. Logic to Generate A1, BHE# and BLE#
BE0#
BE1#
BE1#
BE3#
BE0#
BE0#
BE1#
BE2#
A1
BHE#
BLE# (or A0)
相關PDF資料 |
PDF描述 |
|---|---|
| INTEL486 SX | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| INTEL82801 | 82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | Firmware Hub (FWH) |
| INTELDX2 | High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器) |
| INTELDX4 | Embedded Write-Back Enhanced Processor(32位回復嵌入式增強型處理器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator |
| INTEL82801 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Firmware Hub (FWH) |
| INTELLIGENT CHARGER + 4AA | 制造商:Energizer 功能描述:Bulk |
| INTELLI-INCH-LR-STARTER K | 制造商:ALL MOTION 功能描述:Intelli-Inch Stepper & Controller Starter Kit |
發(fā)布緊急采購，3分鐘左右您將得到回復。
