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參數(shù)資料
| 型號： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 31/48頁 |
| 文件大?。?/td> | 409K |
| 代理商： | INTEL486 GX |
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Embedded Ultra-Low Power Intel486 GX Processor
27
Figure 8. Address Prediction for Burst Transfers (3 of 3)
Next Transfer
MA3=Not [LA3]
MA2=Not [LA2]
MA1=1
Data Cycle
BLAST# = 1
No
END
Yes
This is the last transfer. There is
no need to predict the next
address
Data Cycle
Continued from previous figure
In the figure, MA3, MA2, and MA1 are memory
address bits. LA3 and LA2 are the saved, initial
values of A3 and A2 respectively. The term “MA2 =
NOT [LA2]” means that MA2 is the opposite logic
state as the saved initial A2 value. MA31-MA4 are
derived directly from A31-A4, which remain constant
throughout the burst transfer. M/IO#, W/R#, and
D/C# also remain constant. BLE# (A0) is not shown,
but is always active (LOW) throughout the transfer.
BHE#, also not shown, cannot be predicted for the
last data cycle of a burst transfer and must be
decoded from the byte enable bits for the last burst
cycle (follows BLAST# = 0). Otherwise BHE# is
always active (LOW) throughout the burst. The
processor defines “cacheable data” as the case
where PCD is inactive (LOW) and LOCK# is inactive
(HIGH) and KEN# is active (LOW).
4.6
CPUID Instruction
The embedded ULP Intel486 GX processor supports
the CPUID instruction (see Table 12). Because not
all Intel processors support the CPUID instruction, a
simple test can determine if the instruction is
supported. The test involves the processor’s ID Flag,
which is bit 21 of the EFLAGS register. If software
can change the value of this flag, the CPUID
instruction is available. The actual state of the ID
Flag bit is irrelevant and provides no significance to
the hardware. This bit is cleared (reset to zero) upon
device reset (RESET or SRESET) for compatibility
with Intel486 processor designs that do not support
the CPUID instruction.
CPUID-instruction details are provided here for the
embedded ULP Intel486 GX processor. Refer to
Intel Application Note AP-485
Intel Processor Identi-
fication with the CPUID Instruction
(Order No.
241618) for a description that covers all aspects of
the CPUID instruction and how it pertains to other
Intel processors.
4.6.1
Operation of the CPUID Instruction
The CPUID instruction requires the software
developer to pass an input parameter to the
processor in the EAX register. The processor
response is returned in registers EAX, EBX, EDX,
and ECX.
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