參數(shù)資料
型號(hào)： INTEL486 GX
廠商： Intel Corp.
英文描述： Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器)
中文描述： Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器）
文件頁(yè)數(shù)： 33/48頁(yè)
文件大?。?/td> 409K
代理商： INTEL486 GX
Embedded Ultra-Low Power Intel486 GX Processor
29
4.7
Identification After Reset
Processor Identification
- Upon reset, the EDX register contains the processor signature:
31---------------------------14
4.8
Boundary Scan (JTAG)
4.8.1
Device Identification
Table 13 shows the 32-bit code for the embedded ULP Intel486 GX processor which is loaded into the Device
Identification Register.
13,12
11----8
7----4
3----0
Processor
Signature
EDX
(Do Not Use)
Intel Reserved
0 0
Processor
Type
0 1 0 0
Family
0 0 1 0
Model
XXXX
Stepping
(Intel releases information about stepping numbers as needed)
Table 13. Boundary Scan Component Identification Code
Version
Part Number
Mfg ID
009H = Intel
1
V
CC
0=5V
1=3.3 V
Intel
Architecture
Type
Family
0100 = Intel486
CPU Family
Model
=
embedded ULP
Intel486 GX
processor
31----28
27
26-----------21
20----17
16--------12
11------------1
0
XXXX
1
000001
0100
00000001001
1
(Intel releases information about version numbers as needed)
Boundary Scan Component Identification Code = x828 4013 (Hex)
4.8.2
Boundary Scan Register Bits and Bit
Order
The boundary scan register contains a cell for each
pin as well as cells for control of bidirectional and
three-state pins. There are “Reserved” bits which
correspond to no-connect (N/C) signals of the
embedded ULP Intel486 GX processor. Control
registers
WRCTL,
ABUSCTL,
MISCCTL are used to select the direction of bidirec-
tional or three-state output signal pins. A “1” in these
cells designates that the associated bus or bits are
floated if the pins are three-state, or selected as
input if they are bidirectional.
WRCTL controls D15-D0, DP1 and DP0
ABUSCTL controls A31-A2
BUSCTL,
and
BUSCTL controls ADS#, BLAST#, PLOCK#,
LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#,
D/C#, PWT, and PCD
MISCCTL controls PCHK#, HLDA, and BREQ
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