參數(shù)資料
型號(hào)： INTEL486 GX
廠商： Intel Corp.
英文描述： Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器)
中文描述： Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器）
文件頁(yè)數(shù)： 21/48頁(yè)
文件大小： 409K
代理商： INTEL486 GX
Embedded Ultra-Low Power Intel486 GX Processor
17
Figure 4. Stop Clock State Diagram with Typical Power Consumption Values
4 Auto HALT
Power Down State
CLK Running
40 - 85 mWatts
5 Stop Clock Snoop State
One Clock PowerUp
Perform Cache Invalidation
1 Normal State
Normal Execution
2 Stop Grant State
CLK Running
40 - 85 mWatts
3 Stop Clock State
Internal Powerdown
CLK Stopped
~ 60 μWatts
EADS#
STPCLK#
deasserted
Stop CLK
Start CLK
plus DDL Startup
Latency
STPCLK# asserted
and Stop Grant bus
cycle generated
STPCLK# asserted and
Stop Grant bus cycle generated
STPCLK# deasserted and
HALT bus cycle generated
HALT asserted and
HALT bus cycle
generated
INTR, NMI, SMI#
RESET, SRESET
EADS#
4.3
Level-Keeper Circuits
To obtain the lowest possible power consumption
during the Stop Grant and Stop Clock states, system
designers must ensure that:
input signals with pull-up resistors are not driven
LOW
input signals with pull-down resistors are not
driven HIGH
See Table 8, Input Pins (pg. 14) for the list of signals
with internal pull-up and pull-down resistors.
All other input pins except A31-A4, D15-D0, DP1,
and DP0 must be driven to the power supply rails to
ensure lowest possible current consumption.
During the Stop Grant and Stop Clock states, most
processor output signals maintain their previous
condition, which is the level they held when entering
the Stop Grant state. In response to HOLD driven
active during the Stop Grant state when the CLK
input is running, the embedded ULP Intel486 GX
processor generates HLDA and floats all output and
input/output signals which are floated during the
HOLD/HLDA state. When HOLD is deasserted,
processor signals which maintain their previous state
return to the state they were in prior to the
HOLD/HLDA sequence.
The data bus (D15-D0) and parity bits also maintain
their previous states during the Stop Grant and Stop
Clock states, but do so differently, as described in
the following paragraphs.
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