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參數(shù)資料
| 型號： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 12/48頁 |
| 文件大?。?/td> | 409K |
| 代理商： | INTEL486 GX |
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Embedded Ultra-Low Power Intel486 GX Processor
8
PCHK#
O
Parity Status
is driven on the PCHK# pin the clock after ready for read operations.
The parity status is for data sampled at the end of the previous clock. A parity error
is indicated by PCHK# being LOW. Parity status is only checked for enabled bytes
as indicated by the byte enable signals. PCHK# is valid only in the clock
immediately after read data is returned to the processor. At all other times PCHK#
is inactive (HIGH). PCHK# is never floated.
BUS CYCLE DEFINITION
M/IO#
D/C#
W/R#
O
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
HALT/Special Cycle
Cycle Name
BE3# - BE0#
Shutdown
1110
HALT
1011
Stop Grant bus cycle
1011
LOCK#
O
Bus Lock
ndicates that the current bus cycle is locked. The embedded ULP
Intel486 GX processor does not allow a bus hold when LOCK# is asserted
(address holds are allowed). LOCK# goes active in the first clock of the first locked
bus cycle and goes inactive after the last clock of the last locked bus cycle. The
last locked cycle ends when Ready is returned. LOCK# is active LOW and not
driven during bus hold. Locked read cycles are not transformed into cache fill
cycles when KEN# is returned active.
PLOCK#
O
Pseudo-Lock
indicates that the current bus transaction requires more than one
bus cycle to complete. For the embedded ULP Intel486 GX processor, examples of
such operations are segment table descriptor reads (64 bits) and cache line fills
(128 bits).
The embedded ULP Intel486 GX processor drives PLOCK# active until the
addresses for the last bus cycle of the transaction are driven, regardless of
whether RDY# or BRDY# have been returned.
PLOCK# should be sampled only in the clock in which Ready is returned. PLOCK#
is active LOW and is not driven during bus hold.
BUS CONTROL
ADS#
O
Address Status
output indicates that a valid bus cycle definition and address are
available on the cycle definition lines and address bus. ADS# is driven active in the
same clock in which the addresses are driven. ADS# is active LOW and not driven
during bus hold.
O
O
Memory/Input-Output
,
Data/Control
and
Write/Read
ines are the primary bus
definition signals. These signals are driven valid as the ADS# signal is asserted.
M/IO#
D/C#
W/R#
Bus Cycle Initiated
Interrupt Acknowledge
HALT/Special Cycle (see details below)
I/O Read
I/O Write
Code Read
Reserved
Memory Read
Memory Write
A4-A2
000
000
100
Table 4. Embedded ULP Intel486
GX Processor Pin Descriptions
(Sheet 2 of 6)
Symbol
Type
Name and Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| INTEL486 SX | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| INTEL82801 | 82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | Firmware Hub (FWH) |
| INTELDX2 | High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器) |
| INTELDX4 | Embedded Write-Back Enhanced Processor(32位回復嵌入式增強型處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
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| INTEL740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator |
| INTEL82801 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Firmware Hub (FWH) |
| INTELLIGENT CHARGER + 4AA | 制造商:Energizer 功能描述:Bulk |
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