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參數(shù)資料
| 型號： | INTELDX4 |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded Write-Back Enhanced Processor(32位回復(fù)嵌入式增強型處理器) |
| 中文描述： | 嵌入式回寫增強型處理器（32位回復(fù)嵌入式增強型處理器） |
| 文件頁數(shù)： | 21/50頁 |
| 文件大?。?/td> | 534K |
| 代理商： | INTELDX4 |
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Embedded Write-Back Enhanced IntelDX4 Processor
17
BUS CYCLE DEFINITION
M/IO#
D/C#
W/R#
O
O
O
Memory/Input-Output
,
Data/Control
and
Write/Read
ines are the primary bus
definition signals. These signals are driven valid as the ADS# signal is asserted.
M/IO#
D/C#
W/R#
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
HALT/Special Cycle
Cycle Name
BE3# - BE0#
Shutdown
1110
HALT
1011
Stop Grant bus cycle
1011
Bus Lock
ndicates that the current bus cycle is locked. The Embedded Write-
Back Enhanced IntelDX4 processor does not allow a bus hold when LOCK# is
asserted (address holds are allowed). LOCK# goes active in the first clock of the
first locked bus cycle and goes inactive after the last clock of the last locked bus
cycle. The last locked cycle ends when Ready is returned. LOCK# is active LOW
and not driven during bus hold. Locked read cycles are not transformed into cache
fill cycles when KEN# is returned active.
Pseudo-Lock
indicates that the current bus transaction requires more than one
bus cycle to complete. For the Embedded Write-Back Enhanced IntelDX4
processor, examples of such operations are segment table descriptor reads (64
bits) and cache line fills (128 bits). For Intel486 processors with on-chip Floating-
Point Unit, floating-point long reads and writes (64 bits) also require more than one
bus cycle to complete.
The Embedded Write-Back Enhanced IntelDX4 processor drives PLOCK# active
until the addresses for the last bus cycle of the transaction are driven, regardless of
whether RDY# or BRDY# have been returned.
Normally PLOCK# and BLAST# are inverse of each other. However, during the
first bus cycle of a 64-bit floating-point write (for Intel486 processors with on-chip
Floating-Point Unit) both PLOCK# and BLAST# are asserted.
PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be
sampled only in the clock in which Ready is returned. PLOCK# is active LOW and
is not driven during bus hold.
Bus Cycle Initiated
Interrupt Acknowledge
HALT/Special Cycle (see details below)
I/O Read
I/O Write
Code Read
Reserved
Memory Read
Memory Write
A4-A2
000
000
100
LOCK#
O
PLOCK#
O
BUS CONTROL
ADS#
O
Address Status
output indicates that a valid bus cycle definition and address are
available on the cycle definition lines and address bus. ADS# is driven active in the
same clock in which the addresses are driven. ADS# is active LOW and not driven
during bus hold.
Table 8.
Embedded Write-Back Enhanced IntelDX4 Processor Pin Descriptions
(Sheet 2 of 8)
Symbol
Type
Name and Function
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