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參數(shù)資料
| 型號(hào)： | INTELDX4 |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded Write-Back Enhanced Processor(32位回復(fù)嵌入式增強(qiáng)型處理器) |
| 中文描述： | 嵌入式回寫增強(qiáng)型處理器（32位回復(fù)嵌入式增強(qiáng)型處理器） |
| 文件頁數(shù)： | 30/50頁 |
| 文件大?。?/td> | 534K |
| 代理商： | INTELDX4 |
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Embedded Write-Back Enhanced IntelDX4 Processor
26
WB/WT#
HIGH/LOW
Synchronous
Pull-Down
Pull-Up
1
CLKMUL
HIGH
TCK
HIGH
Pull-Up
TDI
HIGH
Pull-Up
TMS
HIGH
Pull-Up
Table 12. Input Pins
(Sheet 2 of 2)
Name
Active Level
Synchronous/
Asynchronous
Internal Pull-Up/
Pull-Down
NOTE:
1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-K
pull-
up resistor is needed if the STPCLK# pin is unused. CLKMUL must be driven to a valid logic level. If tied HIGH, an external
10-K
pull-up resistor is recommended.
4.0
ARCHITECTURAL AND
FUNCTIONAL OVERVIEW
The Embedded Write-Back Enhanced IntelDX4
processor architecture is essentially the same as the
IntelDX4 processor. Refer to the Embedded
Intel486 Processor Family Developer’s Manual
(273021)
The Embedded Write-Back Enhanced IntelDX4
processor has one pin reserved for possible future
use. This pin, an input signal, is called RESERVED#
and must be connected to a 10-K
pull-up resistor.
The pull-up resistor must be connected only to the
RESERVED# pin.
Do not share this resistor with
other pins requiring pull-ups.
4.1
CPUID Instruction
The Embedded Write-Back Enhanced IntelDX4
processor supports the CPUID instruction (see Table
13). Because not all Intel processors support the
CPUID instruction, a simple test can determine if the
instruction is supported. The test involves the
processor’s ID Flag, which is bit 21 of the EFLAGS
register. If software can change the value of this flag,
the CPUID instruction is available. The actual state
of the ID Flag bit is irrelevant and provides no signifi-
cance to the hardware. This bit is cleared (reset to
zero) upon device reset (RESET or SRESET) for
compatibility with Intel486 processor designs that do
not support the CPUID instruction.
CPUID-instruction details are provided here for the
Embedded
Write-Back
processor. Refer to Intel Application Note AP-485
Intel Processor Identification with the CPUID
Instruction
(Order No. 241618) for a description that
covers all aspects of the CPUID instruction and how
it pertains to other Intel processors.
Enhanced
IntelDX4
4.1.1
Operation of the CPUID Instruction
The CPUID instruction requires the software
developer to pass an input parameter to the
processor in the EAX register. The processor
response is returned in registers EAX, EBX, EDX,
and ECX.
Table 13. CPUID Instruction Description
OP CODE
Instruction
Processor
Core Clocks
Parameter passed in
EAX
(Input Value)
Description
0F A2
CPUID
9
14
9
0
1
Vendor (Intel) ID String
Processor Identification
Undefined (Do Not Use)
> 1
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