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參數(shù)資料
| 型號： | INTELDX4 |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded Write-Back Enhanced Processor(32位回復嵌入式增強型處理器) |
| 中文描述： | 嵌入式回寫增強型處理器（32位回復嵌入式增強型處理器） |
| 文件頁數(shù)： | 28/50頁 |
| 文件大小： | 534K |
| 代理商： | INTELDX4 |
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Embedded Write-Back Enhanced IntelDX4 Processor
24
Table 9. Output Pins
Name
Active Level
Output Signal
Floated During
Address Hold
Floated During
Bus Hold
During Stop Grant and
Stop Clock States
Previous State
1
BREQ
HIGH
HLDA
HIGH
As per HOLD
BE3#-BE0#
LOW
Previous State
PWT, PCD
HIGH
Previous State
W/R#, M/IO#, D/C#
HIGH/LOW
Previous State
LOCK#
LOW
HIGH (inactive)
PLOCK#
LOW
HIGH (inactive)
ADS#
LOW
HIGH (inactive)
BLAST#
LOW
Previous State
PCHK#
LOW
Previous State
FERR#
LOW
Previous State
A3-A2
HIGH
Previous State
SMIACT#
LOW
Previous State
HIGH
2
HIGH
2
CACHE#
LOW
HITM#
LOW
VOLDET
LOW
LOW
NOTES:
1.
The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before the pro-
cessor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
2. For the case of snoop cycles (via EADS#) during Stop Grant state, CACHE# and HITM# can go active depending on the
snoop hit in the internal cache.
Table 10. Input/Output Pins
Name
Active Level
Output Signal
Floated During
Address Hold
Floated During
Bus Hold
During Stop Grant and
Stop Clock States
D31-D0
HIGH
Floated
DP3–DP0
HIGH
Floated
A31-A4
HIGH
Previous State
NOTE:
processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before the
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