參數(shù)資料
型號： INTELDX4
廠商： Intel Corp.
英文描述： Embedded Write-Back Enhanced Processor(32位回復嵌入式增強型處理器)
中文描述： 嵌入式回寫增強型處理器（32位回復嵌入式增強型處理器）
文件頁數(shù)： 3/50頁
文件大小： 534K
代理商： INTELDX4
Contents
iii
EMBEDDED WRITE-BACK ENHANCED
IntelDX4 PROCESSOR
1.0 INTRODUCTION ........................................................................................................................................1
1.1 Features .............................................................................................................................................1
1.2 Family Members .................................................................................................................................2
2.0 HOW TO USE THIS DOCUMENT .............................................................................................................3
3.0 PIN DESCRIPTIONS .................................................................................................................................3
3.1 Pin Assignments .................................................................................................................................3
3.2 Pin Quick Reference .........................................................................................................................16
4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW .............................................................................26
4.1 CPUID Instruction .............................................................................................................................26
4.1.1 Operation of the CPUID Instruction .......................................................................................26
4.2 Identification After Reset ..................................................................................................................28
4.3 Boundary Scan (JTAG) ....................................................................................................................28
4.3.1 Device Identification ...............................................................................................................28
4.3.2 Boundary Scan Register Bits and Bit Order ...........................................................................29
5.0 ELECTRICAL SPECIFICATIONS ...........................................................................................................30
5.1 Maximum Ratings .............................................................................................................................30
5.2 DC Specifications .............................................................................................................................30
5.3 AC Specifications .............................................................................................................................33
5.4 Capacitive Derating Curves ..............................................................................................................40
6.0 MECHANICAL DATA ..............................................................................................................................42
6.1 Package Dimensions ........................................................................................................................42
6.2 Package Thermal Specifications ......................................................................................................44
FIGURES
Figure 1.
Figure 2.
Embedded Write-Back Enhanced IntelDX4
Processor Block Diagram ................................... i
Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced
IntelDX4 Processor ................................................................................................................4
Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced
IntelDX4 Processor ..............................................................................................................10
CLK Waveform ........................................................................................................................36
Input Setup and Hold Timing ...................................................................................................36
Input Setup and Hold Timing ...................................................................................................37
PCHK# Valid Delay Timing ......................................................................................................37
Output Valid Delay Timing .......................................................................................................38
Maximum Float Delay Timing ..................................................................................................38
TCK Waveform ........................................................................................................................39
Test Signal Timing Diagram ....................................................................................................39
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
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