參數(shù)資料
型號(hào)： IS43R16800A1
廠商： Integrated Silicon Solution, Inc.
英文描述： 8Meg x 16 128-MBIT DDR SDRAM
中文描述： 8Meg × 16的128 - Mbit DDR SDRAM內(nèi)存
文件頁(yè)數(shù)： 44/72頁(yè)
文件大?。?/td> 2174K
代理商： IS43R16800A1
44
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/17/06
ISSI
IS43R16800A1
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
CS
RAS
CAS
WE
Command
Action
Notes
Any
H
X
X
X
Deselect
NOP. Continue previous operation
1-6
L
H
H
H
No Operation
NOP. Continue previous operation
1-6
Idle
L
L
H
H
Active
Select and activate row
1-6
L
L
L
H
Auto Refresh
1-7
L
L
L
L
Mode Register Set
1-7
Row Active
L
H
L
H
Read
Select column and start Read burst
1-6, 10
L
H
L
L
Write
Select column and start Write burst
1-6, 10
L
L
H
L
Precharge
Deactivate row in bank(s)
1-6, 8
Read
(Auto Precharge
Disabled)
L
H
L
H
Read
Select column and start new Read burst
1-6, 10
L
L
H
L
Precharge
Truncate Read burst, start Precharge
1-6, 8
L
H
H
L
Burst Terminate
Burst Terminate
1-6, 9
Write
(Auto Precharge
Disabled)
L
H
L
H
Read
Select column and start Read burst
1-6, 10, 11
L
H
L
L
Write
Select column and start Write burst
1-6, 10
L
L
H
L
Precharge
Truncate Write burst, start Precharge
1-6, 8, 11
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t
XSNR /
t
XSRD
has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and t
RP
has been met.
Row Active:
A row in the bank has been activated, and t
RCD
has been met. No data bursts/accesses and no register accesses are in
progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Precharging:
Starts with registration of a Precharge command and ends when t
RP
is met. Once t
RP
is met, the bank is in the idle
state.
Row Activating: Starts with registration of an Active command and ends when t
RCD
is met. Once t
RCD
is met, the bank is in the “row
active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t
RP
has been
met. Once t
RP
is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when t
RP
has been
met. Once t
RP
is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.
5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states.
Refreshing:
Starts with registration of an Auto Refresh command and ends when t
RFC
is met. Once t
RFC
is met, the DDR SDRAM is
in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t
MRD
has been met. Once t
MRD
is
met, the DDR SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when t
RP
is met. Once t
RP
is met, all banks is in the idle
state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
11. Requires appropriate DM masking.
相關(guān)PDF資料
PDF描述
IS43R16800A1-5TL 8Meg x 16 128-MBIT DDR SDRAM
IS43R32400A 4Meg x 32 128-MBIT DDR SDRAM
IS43R32400A-5B 4Meg x 32 128-MBIT DDR SDRAM
IS43R32400A-5BL 4Meg x 32 128-MBIT DDR SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS43R16800A1-5TL 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:8Meg x 16 128-MBIT DDR SDRAM
IS43R16800A-5T 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R16800A-5TL 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R16800A-5TL-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R16800A-5T-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
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