參數(shù)資料
型號(hào)： IS75V16F128GS32-7065BI
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： 存儲(chǔ)器
英文描述： 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA107
封裝： 9 X 10 MM, 0.80 MM PITCH, FBGA-107
文件頁(yè)數(shù)： 4/52頁(yè)
文件大?。?/td> 264K
代理商： IS75V16F128GS32-7065BI
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00D
03/24/03
IS75V16F128GS32
ISSI
OPERATION
(1,2)
CE
f1
CE
f2
CE1
r CE2r
OEWE LB
s
UB
s
PE
A
21
-A
0
DQ
7
-DQ
0
DQ
15
-DQ
8
X
X
X
H
X
H
X
X
H
X
(10)
H
X
X
H
X
H
X
X
H
X
RESET1RESET2 WP
/ACC
(12)
Full Standby
Output Disable
(3)
H
H
L
H
H
H
H
L
H
L
H
H
H
H
H
H
X
H
H
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
H
H
H
H
H
H
H
H
X
X
X
X
Read from FLASH 1
(4)
L
H
H
H
L
H
X
X
H
Valid
D
OUT
D
OUT
H
H
X
Read from FLASH 2
(4)
H
Write to FLASH 1
Write to FLASH 2
Read from PSRAM
(5)
H
Write to PSRAM
L
H
L
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
L
L
H
L
L
L
X
X
X
L
(9)
L
H
L
X
X
X
L
(9)
L
L
H
H
H
H
H
H
H
H
Valid
Valid
Valid
Valid
Valid
Valid
Valid
D
OUT
D
IN
D
IN
D
OUT
D
IN
High-Z
D
IN
D
OUT
D
IN
D
IN
D
OUT
D
IN
D
IN
High-Z
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
L
H
H
H
H
FLASH 1Temporary
Sector Group
Unprotection
(6)
FLASH 2 Temporary
Sector Group
Unprotection
(6)
FLASH 1
Hardware Reset
FLASH 2
Hardware Reset
Boot Block Sector
Write Protection
PSRAM Power
(7)
Down Program
PSRAM No Read
PSRAM
Power Down
(8)
X
X
X
X
X
X
X
X
X
X
X
X
V
ID
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
ID
X
X
X
H
H
X
X
X
X
X
X
High-Z
High-Z
L
X
X
X
X
H
H
X
X
X
X
X
X
High-Z
High-Z
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
L
H
H
X
L
X
H
X
H
X
H
L
H
Valid
Valid
High-Z
High-Z
High-Z
High-Z
H
H
H
H
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “DC CHARACTERISTICS” for voltage levels.
Notes:
1. Other operations except for indicated this column are prohibited.
2. Do not apply
CE
f = VIL,
CE
1r = VIL and CE2r = VIH all at once.
3. PSRAM Output Disable condition should not be kept longer than 1ms.
4.
WE
can be VIL if
OE
is VIL,
OE
at VIH initiates the write operations.
5. PSRAM
LB
,
UB
control at Read operation is not supported.
6. It is also used for the extended sector group protections.
7. The PSRAM Power Down Program can be performed one time after compliance of Power-UP timings and it should not be re-
programmed after regular Read or Write.
8. PSRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IPDr current and data retention
depends on the selection of Power Down Program.
9. Either or both
LB
and
UB
must be Low for PSRAM Read Operation.
10. Can be either VIL or VIH but must be valid before Read or Write.
11. See “ PSRAM Power Down Program Key Table “ located in the next page.
12. Protect “ outer most “ 2x8K bytes ( 4 words ) on both ends of the boot block sectors.
DEVICE BUS OPERATION
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