參數(shù)資料
型號: IS75V16F128GS32-7065BI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: 存儲器
英文描述: 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA107
封裝: 9 X 10 MM, 0.80 MM PITCH, FBGA-107
文件頁數(shù): 2/52頁
文件大?。?/td> 264K
代理商: IS75V16F128GS32-7065BI
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00D
03/24/03
IS75V16F128GS32
ISSI
GENERAL DESCRIPTION
This 107-ball MCP is a space-saving combination of 3 memories: two 64Mbit Flash and one 32Mbit Pseudo SRAM.
Each 64Mbit Flash (Flash1 and Flash 2) contains 4,194,304 words and the 32Mbit PSRAM contains 2,097,152
words. Each word is 16 bits wide. Data lines DQ0-DQ15 handle the access for all three memories. Write Enable,
Output Enable, and A0-A20 are shared among the three memories. Single Byte data on the PSRAM can be
accessed one at a time on DQ0-DQ7 or DQ8-DQ15 by using
LB
or
UB
, respectively.
The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations.
The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM
programmer.
The flash chips are compatible with the JEDEC Flash command set standard. The flash access time is 70ns and the
PSRAM access time is 65ns.
Each Flash memory implements an architecture composed of two virtual banks that allows simultaneous operation on
each bank. Optimized performance can be achieved by first initializing a program or erase function in one bank, then
immediately starting a read from the other bank. Both operations would then be operating simultaneously on the same
chip, with zero latency.
MCP BLOCK DIAGRAM
GND
GND
V
CCf2
RY/
BY
2
32-MBIT
PSRAM
32-MBIT
Flash Memory
(Flash 2)
DQ0-DQ15
LB
UB
WE
OE
CE1
r
CE2r
PE
A0-A20
V
CCr
A0-A21
CE
f
2
RESET
2
WP
/ACC
64-MBIT
Flash Memory
(Flash 1)
A0-A21
RESET
1
CE
f
1
GND
V
CCf1
RY/
BY
1
A0-A21
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