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參數(shù)資料
| 型號(hào)： | K7R323682 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM |
| 中文描述： | 1Mx36 |
| 文件頁(yè)數(shù)： | 12/19頁(yè) |
| 文件大?。?/td> | 201K |
| 代理商： | K7R323682 |
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1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
- 2 -
Rev 2.0
Dec. 2003
K7R323682M
K7R321882M
K7R320982M
1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDRTM II b2 SRAM
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future
freguency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O
.
Separate independent read and write data ports
with concurrent read and write operation
HSTL I/O
Full data coherency, providing most current data .
Synchronous pipeline read with self timed early write.
Registered address, control and data input/output.
DDR(Double Data Rate) Interface on read and write ports.
Fixed 2-bit burst for both read and write operation.
Clock-stop supports to reduce current.
Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
Two echo clocks (CQ and CQ) to enhance output data
traceability.
Single address bus.
Byte write (x9, x18, x36) function.
Sepatate read/write control pin(R and W)
Simple depth expansion with no data contention.
Programmable output impenance.
JTAG 1149.1 compatible test access port.
165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
R
ADDRESS
W
C
D(Data in)
ADD
REG
DATA
REG
CLK
GEN
CTRL
LOGIC
1Mx36
(2Mx18)
MEMORY
ARRAY
WRITE DRIVER
K
BWX
36 (or 18)
4(or 2)
Organization
Part
Number
Cycle
Time
Access
Time
Unit
X36
K7R323682M-FC20
5.0
0.45
ns
K7R323682M-FC16
6.0
0.50
ns
X18
K7R321882M-FC20
5.0
0.45
ns
K7R321882M-FC16
6.0
0.50
ns
X9
K7R320982M-FC20
5.0
0.45
ns
K7R320982M-FC16
6.0
0.50
ns
SELECT OUTPUT CONTROL
S
E
N
S
E
A
M
P
S
W
R
IT
E
/R
E
A
D
E
C
O
D
E
O
U
T
P
U
T
R
E
G
O
U
T
P
U
T
S
E
L
E
C
T
O
U
T
P
U
T
D
R
IV
E
R
Notes: 1. Numbers in ( ) are for x18 device, x9 device also the same with appropriate adjustments of depth and width.
72
19
19 (or 20)
36 (or 18)
Q(Data Out)
36 (or 18)
72
(Echo Clock out)
CQ, CQ
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung techno logy.
(or 20)
(or 36)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7R323682C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 & 4Mx9 QDR II b2 SRAM |
| K7R323682C-EC25000 | 制造商:Samsung SDI 功能描述: |
| K7R323682C-FC16000 | 制造商:Samsung 功能描述:32M 32MSYNC QUAD DATA RATE II X36 FBGA - Trays |
| K7R323682C-FC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 & 4Mx9 QDR II b2 SRAM |
| K7R323682C-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 & 4Mx9 QDR II b2 SRAM |
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