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參數(shù)資料
| 型號： | K7R323682 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM |
| 中文描述： | 1Mx36 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 201K |
| 代理商： | K7R323682 |
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
- 7 -
Rev 2.0
Dec. 2003
K7R323682M
K7R321882M
K7R320982M
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with following K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit or 9-bit or 8-bit data words with each write command.
The first "early" data is transfered and registered in to the device synchronous with same K clock rising edge with W presented.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "early writed" data is presented to the device on every rising edge of both K and K clocks.
When the W is disabled, the K7R323682M,K7R321882M and K7R320982M will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7R323682M, K7R321882M and K7R320982M support byte write operations.
With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented.
In K7R321882M, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7R323682M BW2 controls write operation to D18:D26, BW 3 controls write operation to D27:D35.
And in K7R320982M BW controls write operation to D0:D8.
Write Operations
Depth Expansion
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250
resistor will give an output impedance of 50.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behav-
ior in the SRAM.
To guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
K7R323682M,K7R321882M and K7R320982M can be operated with the single clock pair K and K,
insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device can’t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
Clock Consideration
K7R323682M,K7R321882M and K7R320982M utlizes internal DLL(Delay-Locked Loops) for maximum output
data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Single Clock Mode
Programmable Impedance Output Buffer Operation
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.
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| K7R323682C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 & 4Mx9 QDR II b2 SRAM |
| K7R323682C-EC25000 | 制造商:Samsung SDI 功能描述: |
| K7R323682C-FC16000 | 制造商:Samsung 功能描述:32M 32MSYNC QUAD DATA RATE II X36 FBGA - Trays |
| K7R323682C-FC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 & 4Mx9 QDR II b2 SRAM |
| K7R323682C-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 & 4Mx9 QDR II b2 SRAM |
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