Functional Description and Application Information
Background Debug Module (S12SBDMV1)
MM912F634
Freescale Semiconductor
205
selected.
Figure 61. BDM Command Structure
4.30.4.6
BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which
selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
BDM.
The BDM serial interface is timed based on DCO clock or external reference clock depending on the configuration used (refer to
the CRG Block Guide for more details), which gets divided by five. This clock will be referred to as the target clock in the following
explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate
the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data transfers the most
significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between the falling
edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level.
Since R-C rise time could be unacceptably long, the target system and host provide brief driven high (speedup) pulses to drive
BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases.
the host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can
take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of
the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle
earlier. Synchronization between the host and target is established in this manner at the start of every bit time.
Figure 62 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host
is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target
recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD
Hardware
Firmware
GO,
48-BC
BC = Bus Clock Cycles
Command
Address
150-BC
Delay
Next
DELAY
8 Bits
AT ~16 TC/Bit
16 Bits
AT ~16 TC/Bit
16 Bits
AT ~16 TC/Bit
Command
Address
Data
Next
Data
Read
Write
Read
Write
TRACE
Command
Next
Command
Data
76-BC
Delay
Next
Command
150-BC
Delay
36-BC
DELAY
Command
Data
Next
Command
TC = Target Clock Cycles