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參數(shù)資料
| 型號(hào)： | KIT912F634EVME |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 18/339頁(yè) |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MM912F634 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | MM912F634 |
| 所含物品： | 板，線纜，CD |
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Functional Description and Application Information
Serial Communication Interface (S08SCIV4)
MM912F634
Freescale Semiconductor
114
4.15.2.3
SCI Control Register 2 (SCIC2)
This register can be read or written at any time.
Table 130. SCI Control Register 2 (SCIC2)
Offset(102) 0x43
Access: User read/write
76
543
210
R
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
W
Reset
0
000
00
Note:
102. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 131. SCIC2 Field Descriptions
Field
Description
7
TIE
Transmit Interrupt Enable (for TDRE)
0 Hardware interrupts from TDRE disabled (use polling).
1 Hardware interrupt requested when TDRE flag is 1.
6
TCIE
Transmission Complete Interrupt Enable (for TC)
0 Hardware interrupts from TC disabled (use polling).
1 Hardware interrupt requested when TC flag is 1.
5
RIE
Receiver Interrupt Enable (for RDRF)
0 Hardware interrupts from RDRF disabled (use polling).
1 Hardware interrupt requested when RDRF flag is 1.
4
LIE
Idle Line Interrupt Enable (for IDLE)
0 Hardware interrupts from IDLE disabled (use polling).
1 Hardware interrupt requested when IDLE flag is 1.
3
TE
Transmitter Enable
0 Transmitter off.
1 Transmitter on.
TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single
SCI communication line (TxD pin).
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress. Refer to
Section 4.15.3.2.1, “Send Break and Queued Idle"” for more details.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued break character
finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
2
RE
Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS = 1
the RxD pin reverts to being a general-purpose I/O pin even if RE = 1.
0 Receiver off.
1 Receiver on.
1
RWU
Receiver Wake-up Control — This bit can be written to 1 to place the SCI receiver in a standby state where it waits for
automatic hardware detection of a selected wake-up condition. The wake-up condition is either an idle line between messages
(WAKE = 0, idle-line wake-up), or a logic 1 in the most significant data bit in a character (WAKE = 1, address-mark wake-up).
Application software sets RWU and (normally) a selected hardware condition automatically clears RWU. Refer to
Section 4.15.3.3.2, “Receiver Wake-up Operation"” for more details.
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wake-up condition.
0
SBK
Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break
characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of
the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before
software clears SBK. Refer to Section 4.15.3.2.1, “Send Break and Queued Idle"” for more details.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
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