Functional Description and Application Information
S12S Debug (S12SDBGV1) Module
MM912F634
Freescale Semiconductor
227
Table 293 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the corresponding TAG bit
is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue.
4.31.3.2.8.2
Debug Comparator Address High Register (DBGXAH)
The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window from 0x0028 to 0x002F.
5
TAG
Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate state sequencer
transition or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the
instruction queue.
0 Allow state sequencer transition immediately on match
1 On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition
4
BRK
Break— This bit controls whether a comparator match terminates a debug session immediately, independent of state
sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bit
DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active,
is terminated and the module disarmed.
3
RW
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated
comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same register is set.
0 Write cycle will be matched
1 Read cycle will be matched
2
RWE
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated
comparator.This bit is ignored if the TAG bit in the same register is set
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
0
COMPE
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled
Table 293. Read or Write Comparison Logic Table
RWE Bit
RW Bit
RW Signal
Comment
0
x
0
RW not used in comparison
0
x
1
RW not used in comparison
1
0
Write data bus
1
0
1
No match
11
0
No match
1
Read data bus
Table 294. Debug Comparator Address High Register (DBGXAH)
Address: 0x0029
7
6
5
432
10
R
0
000
0
Bit 17
Bit 16
W
Reset
0
000
00
0
Table 295. Comparator Address Register Visibility
COMRV
Visible Comparator
00
DBGAAH, DBGAAM, DBGAAL
Table 292. DBGXCTL Field Descriptions (continued)
Field
Description