參數(shù)資料
型號: KM44S16030B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 4Bit x 4 Banks Synchronous DRAM(4M x 4位 x 4組同步動態(tài)RAM)
中文描述: 4米× 4位× 4銀行同步DRAM(4米× 4位× 4組同步動態(tài)RAM)的
文件頁數(shù): 30/43頁
文件大?。?/td> 625K
代理商: KM44S16030B
TIMING DIAGRAM - III
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ELECTRONICS
REV. 2 Mar. '98
Read & Write Cycle at Same Bank @Burst Length=4
HIGH
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(t
3. Access time from Row active command. t
CC
*(t
RCD
+ CAS latency - 1) + t
SAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
SHZ
) after the clcok.
*Note 1
tRC
tRCD
*Note 2
tRDL
tRDL
tSHZ
*Note 4
tSHZ
*Note 4
tOH
tRAC
*Note 3
tSAC
tSAC
tRAC
*Note 3
tOH
BA
0
BA
1
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
Ra
Rb
Qa0
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Db0
Db1
Db2
Db3
Ra
Ca
Rb
Cb
WE
DQM
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
相關(guān)PDF資料
PDF描述
KM44S16030C 4M x 4Bit x 4 Banks Synchronous DRAM(4M x 4位 x 4組同步動態(tài)RAM)
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