參數(shù)資料
型號(hào): KM44S16030B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 4Bit x 4 Banks Synchronous DRAM(4M x 4位 x 4組同步動(dòng)態(tài)RAM)
中文描述: 4米× 4位× 4銀行同步DRAM(4米× 4位× 4組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 37/43頁(yè)
文件大?。?/td> 625K
代理商: KM44S16030B
TIMING DIAGRAM - III
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ELECTRONICS
REV. 2 Mar. '98
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
Ra
Row Active
Clock
Suspension
Read
Write
DQM
: Don't care
Clock
Suspension
Read
*Note 1
tSHZ
tSHZ
Write
DQM
Write
Read DQM
*Note :
1. DQM is needed to prevent bus contention.
BA
0
BA
1
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A
10
/AP
Ra
Ca
Cb
Cc
Dc2
Dc0
Qb1
Qb0
Qa3
Qa2
Qa1
Qa0
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