參數(shù)資料
型號: KM44S16030B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 4Bit x 4 Banks Synchronous DRAM(4M x 4位 x 4組同步動態(tài)RAM)
中文描述: 4米× 4位× 4銀行同步DRAM(4米× 4位× 4組同步動態(tài)RAM)的
文件頁數(shù): 33/43頁
文件大小: 625K
代理商: KM44S16030B
TIMING DIAGRAM - III
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ELECTRONICS
REV. 2 Mar. '98
Page Write Cycle at Different Bank @Burst Length=4
HIGH
Row Active
(A-Bank)
Write
(A-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
: Don't care
*Note :
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
Row Active
(B-Bank)
tRDL
Row Active
(C-Bank)
Precharge
(All Banks)
tCDL
Write
(B-Bank)
Write
(C-Bank)
*Note 1
BA
0
BA
1
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A
10
/AP
RAa
RBb
CAa
CBb
RCc
RDd
CCc
CDd
RCc
RDd
RAa
RBb
*Note 2
DAa0
DAa1 DAa2
DAa3
DBb0
DBb1
DBb2 DBb3
DCc0
DCc1
DDd0
DDd1
DDd2
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