參數(shù)資料
型號(hào): KM44S4020CT
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2M x 4Bit x 2 Banks Synchronous DRAM(2M x 4位 x 2組同步動(dòng)態(tài)RAM)
中文描述: 2米x 4位× 2銀行同步DRAM(2米× 4位× 2組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 2/44頁(yè)
文件大?。?/td> 604K
代理商: KM44S4020CT
KM44S4020C
REV. 5 Feb. '98
CMOS SDRAM
The KM44S4020C is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 2,097,152 words by 4 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K Cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2M x 4Bit x 2 Banks Synchronous DRAM
ORDERING INFORMATION
Part No.
Max Freq.
125MHz
100MHz
100MHz
100MHz
Interface
Package
KM44S4020CT-G/F8
KM44S4020CT-G/FH
KM44S4020CT-G/FL
KM44S4020CT-G/F10
LVTTL
44
TSOP(II)
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
2M x 4
2M x 4
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
Timing Register
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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