參數(shù)資料
型號(hào): KM44S4020CT
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2M x 4Bit x 2 Banks Synchronous DRAM(2M x 4位 x 2組同步動(dòng)態(tài)RAM)
中文描述: 2米x 4位× 2銀行同步DRAM(2米× 4位× 2組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 21/44頁(yè)
文件大?。?/td> 604K
代理商: KM44S4020CT
CMOS SDRAM
DEVICE OPERATIONS - I
ELECTRONICS
REV. 4 Feb. '98
*Note :
1. t
RDL
: Last data in to row precharge delay
2. Number of valid output data after row precharge : 0, 1, 2 for CAS Latency =1, 2, 3 respectively.
3. The row active command of the precharge bank can be issued after t
The new read/write command of the other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/other bank is illegal.
RP
from this point.
6. Precharge
D
0
D
1
D
2
CLK
CMD
DQ
WR
PRE
D
3
1) Normal Write (BL=4)
tRDL
Note 2
2) Normal Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
PRE
Q
0
Q
1
Q
2
Q
3
Q
0
Q
1
Q
2
Q
3
1
2
Note 2
7. Auto Precharge
D
0
D
1
D
2
CLK
CMD
DQ
WR
D
3
1) Normal Write (BL=4)
Note 3
Auto Precharge Starts
2) Normal Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
Q
0
Q
1
Q
2
Q
3
Q
0
Q
1
Q
2
Q
3
Note 3
Auto Precharge Starts
相關(guān)PDF資料
PDF描述
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