參數(shù)資料
型號: KM44S4020CT
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2M x 4Bit x 2 Banks Synchronous DRAM(2M x 4位 x 2組同步動態(tài)RAM)
中文描述: 2米x 4位× 2銀行同步DRAM(2米× 4位× 2組同步動態(tài)RAM)的
文件頁數(shù): 22/44頁
文件大小: 604K
代理商: KM44S4020CT
CMOS SDRAM
DEVICE OPERATIONS - I
ELECTRONICS
REV. 4 Feb. '98
*Note :
1. t
RDL
: 1 CLK
2. t
BDL
: 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : Both banks precharge if necessary.
MRS can be issued only at both banks precharge state.
8. Burst Stop & Interrupted by Precharge
D
0
D
1
D
2
CLK
CMD
DQ
WR
PRE
D
3
1) Normal Write (BL=4)
tRDL Note 1
3) Read Interrupted by Precharge (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
PRE
Q
0
Q
1
Q
0
Q
1
1
2
Note 3
9. MRS
CLK
PRE
1) Mode Register Set
D
0
D
1
D
2
CLK
CMD
DQ
WR
STOP
D
3
2) Write Burst Stop (BL=8)
DQM
4) Read Burst Stop (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
STOP
Q
0
Q
1
Q
0
Q
1
1
2
Note 3
MRS
ACT
Note 4
tRP
2CLK
CMD
DQM
tBDL Note 2
D
4
D
5
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