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參數(shù)資料
| 型號： | KS9241B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CD-ROM Decoder(光盤驅(qū)動器解碼器) |
| 中文描述： | 的CD - ROM解碼器（光盤驅(qū)動器解碼器） |
| 文件頁數(shù)： | 20/37頁 |
| 文件大小： | 211K |
| 代理商： | KS9241B |
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KS9241B
CD-ROM DECODER
20
( NP + 43 X MP ) X 2 + a, 0
≤
N
P
≤
42
0
≤
M
P
≤
25
In terms of Q code, the real position of (M
Q
+ 1) th symbol of (N
Q
+ 1) th code at RAM is measured as follows
{( 43 X N
Q
+ 44 X M
Q
)mod 1 1 1 8} X 2 + a, 0
≤
N
Q
≤
25
0
≤
M
Q
≤
42
(N
Q
+ 26 X M
Q
) X 2 + a, 0
≤
N
Q
≤
25
43
≤
M
Q
≤
44
Only, a is
“
0
”
in case of LSB plane and
“
1
”
in case of MSB plane. The detecting correction of KS9241B is
completed by the follwing process. Low order byte of Q code
→
High order byte of Q code
→
Low order byte of P
code
→
High order byte of P code. The erasure correction order is the same as the above. EDC can be performed
after error correction is finished during 1 block correction period.
EDC uses 32-bit CRC in mode 1 from sync to user data and in mode 2 from subheader to user data. EDC code
word should be divided by check Polynomial which is as follows.
P(X) = (X
16
+ X
15
+X
2
+ 1) (X
16
+ X
2
+ X + 1)
During EDC period, the header and subheader are stored at the internal register. After EDC, KS9241B are
designed to generate decode interrupt to micom. The micom reads the header, subheader, DBSPH, DBSPL
registers of the decoded block and various flags which indicates the decoding result.
INTERFACE BLOCK (HOST AND MICOM)
(a) Control signal
Control signal of host interface: /CMD, /HRD, /HWR
But, available only when /HCS pin is
“
L
”
(i) When / CMD =
“
L
”
/ HRD =
“
L
”
/ HWR =
“
H
”
(Status read):
The data applied from micom and written in status register is outputted as host data.
(ii) When / CMD =
“
L
”
/ HRD =
“
H
”
/ HWR =
“
L
”
(Command write):
The data from host is written into command FIFO register.
(iii) When / CMD =
“
H
”
, / HRD =
“
L
”
, / HWR =
“
H
”
(Data read):
Of those read from RAM, the data is sent out through HD0-7 and the erasure frag is out through /HDE
(iv) It is prohibited when / CMD =
“
H
”
, / HRD =
“
H
”
, / HWR =
“
L
”
Control signal of micom interface : MRS, / MRD, /MWR.
But, available only when /MCS pin is
“
L
”
(i) MRS =
“
L
”
, /MR =
“
L
”
, /MWR =
“
H
”
(Reads register
’
s address):
The address values determining internal register are output as micom data. At this time, address is output as the
lower 4-bit of micom data and the higher 4-bit is output as
“
0
”
.
(ii) MRS =
“
L
”
, /MRD =
“
H
”
:, /HWR =
“
L
”
(Writes register
’
s address):
The lower 4-bit of micom data is written to address decoder.
(iii) MRS =
“
H
”
, / MRD =
“
L
”
, /MWR=
“
H
”
(Register read):
The contents of register selected by address decoder is outputted into micom data.
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