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參數(shù)資料
| 型號(hào)： | KS9241B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CD-ROM Decoder(光盤(pán)驅(qū)動(dòng)器解碼器) |
| 中文描述： | 的CD - ROM解碼器（光盤(pán)驅(qū)動(dòng)器解碼器） |
| 文件頁(yè)數(shù)： | 30/37頁(yè) |
| 文件大?。?/td> | 211K |
| 代理商： | KS9241B |
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KS9241B
CD-ROM DECODER
30
HEADERR (Head / Subheader Error) Register
H1ERR - H4ERR:
Error flag about each minutes, seconds, blocks, and mode byte.
SH1ERR - SH2ERR:
Error flag about the byte of file number, channel number, submode number, coding information. In this case, if
only one of 2 bytes is error, the error flag becomes
“
0
”
,and if both of 2 bytes are errors, the error flag becomes
“
1
”
.
FORMAT Register
NDBM1 - NDBM4 (Next Decoding Block Mode):
It indicates the mode byte conditions of the block to be decoded at the next stage.
NDBM1 = Mode byte bit 7 + bit 6 + bit 5 + bit 4 + bit 3 + error flag of mode byte
NDBM2 = Mode byte bit 2 + error flag of mode byte
NDBM3 = Mode byte bit 1 + error flag of mode byte
NDBM4 = Mode byte bit 0 + error flag of mode byte
MODE:
It indicates the mode when the block is decoded, For example, if
“
0
”
, it indicates mode 1 and If
“
1
”
, mode 2.
NOEC (No Error Correction):
If
“
1
”
, the error correction is prohibited.
NDBFM (Next Decoding Block Form):
It indicates the subheader
’
s form bit before the error correction of the block which should be decoded.
And it is valid only when NDBSEF is
“
1
”
.
e. NDBSEF(Next Decoding Block Submode byte Error Flag):
Error flag of submode byte of the subheaders in the block which should be decoded.
STATE 2 Register
DIREN (Decoder Interrupt Register Enable):
If
“
0
”
, the register about Decoder Interrupt is valid.
/LNGWRD (Long word):
“
1
”
, it indicates when the one word period is longer than 192 clock of XIN pin signal, and then the Decoder
operation is not affected by the process.
ECPRC (Error Correction Processing):
If
“
1
”
, it indicates that error correction is being performed.
STATUS Register
It is a register designed to transmit the status data into the the host.
ICONT (Interface Control) Register
CDIEN (Command Interrupt Enable)/
DTIEN (Data Transfer Interrupt Enable)/ DCIEN (Decoder Interrupt Enable): On condition that the
corresponding bit or ISTATE register is
“
0
”
, if the Interrupt Enable bit is
“
1
”
, the /INT pin is
“
L
”
.
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