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參數(shù)資料
| 型號： | KS9241B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CD-ROM Decoder(光盤驅(qū)動器解碼器) |
| 中文描述： | 的CD - ROM解碼器（光盤驅(qū)動器解碼器） |
| 文件頁數(shù)： | 24/37頁 |
| 文件大?。?/td> | 211K |
| 代理商： | KS9241B |
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KS9241B
CD-ROM DECODER
24
(d) Data Transmission
(i) Normal Operation
Normal operation occurs only when /DTWT bit of ICONT register is
“
0
”
and data transmission is available only
when DTUEN bit of ICONT register is
“
1
”
. For data transmission, first, DTUEN bit should be set at
“
1
”
by writing of
micom data, and then the byte number should be registered next into DTBCL. DTBCH registers are transmitted.
Here the data to be registered is the value of the byte number to be registered, minus 1. The maximum amount to
be transmitted is 4096 bytes. After that, the 2 X 9-bit FIFO register for data transmission is cleared by writing into
DTSTR register and / DTOPR bit of ISTATE register becomes
“
0
. Then the /DREN pin becomes
“
L
”
, which
indicates that the data transmission into host is ready. Host is enabled to read data from FIFO only when /DREN
pin is
“
L
”
.
Figure 18.
NOTE:
Condition: /HCS =
“
L
”
, /CMD =
“
L
”
, /HWR =
“
H
”
/MCS =
“
L
”
, /MRD =
“
H
”
invalid data
(Normal Operation Timing> (/DTWT =
“
1
”
)
MRS
/WMR
/DTUOP
/DTOPR
/DREN
/OE
MD7-0
DB7-0.ERF
DTACH.DTACL
DTBCH.DTBCL
/HRD
DB7-0/HDE
DATA FIFO FULL
DATA FIFO EMPTY
/DTE
/DTINT
/WAIT
(/SEL=
“
H
”
)
/WAIT
(/SEL=
“
L
”
)
B2
B3
BB
B4
BB
‘
X
’
‘
X
’
d1
d2
d3
d4
B1
B2
B3
B4
d1
d2
d3
d4
invalid data
invalid data
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