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參數(shù)資料
| 型號(hào)： | KSZ8692XPB |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 16/42頁 |
| 文件大小： | 0K |
| 描述： | IC ARM9 PHY 10/100MBPS 400-PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | KSZx692 |
| 應(yīng)用： | 網(wǎng)絡(luò)和通信 |
| 核心處理器： | ARM9 |
| 程序存儲(chǔ)器類型： | 外部程序存儲(chǔ)器 |
| 控制器系列： | KSZ |
| 接口： | EBI/EMI，以太網(wǎng)，I²C，I²S，PCI，SPI，UART/USART，USB |
| 輸入/輸出數(shù)： | 20 |
| 電源電壓： | 1.235 V ~ 1.365 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BGA |
| 包裝： | 托盤 |
| 供應(yīng)商設(shè)備封裝： | 400-PBGA（24x24） |
| 產(chǎn)品目錄頁面： | 1080 (CN2011-ZH PDF) |
| 其它名稱： | 576-3537 |
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Micrel, Inc.
KSZ8692MPB/KSZ8692XPB
March 2010
23
M9999-031810-4.0
Signal Descriptions by Group
Pin Number
Pin Name
Pin Type
Pin Description
System Interface
R5
RESETN
I
Reset, asserted Low.
RESETN will force the KSZ8692MPB/KSZ8692XPB to reset ARM9 CPU and
all functional blocks. Once asserted, RESETN must remain asserted for a
minimum duration of 256 system clock cycles. When in the reset state, all the
output pins are put into Tri-state and all open drain signals are floated.
N5
WRSTO
O
Watchdog Timer Reset Output
When the Watchdog Timer expires, this signal will be asserted for at least 200
msec.
W1
XCLK2
I
System Clock Input 2.
External crystal or clock input 2. The clock frequency should be 25MHz
±
100ppm.
Y1
XCLK1
I
System Clock Input 1.
Used with XCLK1 pin when other polarity of crystal is needed. This is unused
for a normal clock input.
H19
CLK25MHz
O
25MHz output to external PHY
Y15, Y14
DDCLKO[1:0]
O
DDR Clock Out [1:0].
Output of the internal system clock, it is also used as the clock signal for DDR
interface.
W15, W14
DDCLKON[1:0]
O
The negative of differential pair of DDR Clock Out [1:0].
Output of the internal system clock, it is also used as the clock signal for DDR
interface.
U13
SDCLKEO
O
Clock Enable output for SDRAM (for Power Down Mode)
T7, U7
VREF
I
Reference Voltage for SSTL interface.
Must be half of the voltage for the DDR VDD supply. See EIA/JEDEC standard
EIA/JESD8-9 (Stub series terminated logic for 2.5V, SSTL_2)
W3
SDOCLK
O
DDR Clock Out for loopback from De-skew PLL
Y3
SDICLK
I
DDR Clock In from loopback to De-skew PLL. This pin must connect to
SDOCLK with appropriate de-skew length. See Engineering Evaluation Design
Kit for detailed implementation.
Y17, Y16
DDCLKO[3:2]
O
Factory Reserved
W17, W16
DDCLKON[3:2]
O
Factory Reserved
NAND/SRAM/ROM/EXIO Interface
L2, K1, K2,
J3, H5, H4,
J2, H3, J1,
H2, G5, H1,
G3, G4, G2,
F1, G1, F2,
F3, F5, F4,
E1, E2, E3
SADDR[23..0]
O
SRAM Address Bus.
The 24-bit address bus covers 16M word memory space of
ROM/SRAM/FLASH, and 16M byte external I/O banks.
This address bus is shared between ROM/SRAM/FLASH/EXTIO devices.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8695P | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Multi-Port PCI Gateway Solution(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| KSZ8695PI | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Multi-Port PCI Gateway Solution (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| KSZ8695P-MDP-EVAL | 功能描述:網(wǎng)絡(luò)開發(fā)工具 KSZ88695P-MDP Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| KSZ8695P-MMB-EVAL | 功能描述:網(wǎng)絡(luò)開發(fā)工具 KSZ8695P-MMB Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| KSZ8695PX | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Integrated Multi-Port Gateway Solution w/ Single PCI(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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