參數(shù)資料
型號: KSZ8692XPB
廠商: Micrel Inc
文件頁數(shù): 21/42頁
文件大小: 0K
描述: IC ARM9 PHY 10/100MBPS 400-PBGA
標準包裝: 40
系列: KSZx692
應用: 網絡和通信
核心處理器: ARM9
程序存儲器類型: 外部程序存儲器
控制器系列: KSZ
接口: EBI/EMI,以太網,I²C,I²S,PCI,SPI,UART/USART,USB
輸入/輸出數(shù): 20
電源電壓: 1.235 V ~ 1.365 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 400-BGA
包裝: 托盤
供應商設備封裝: 400-PBGA(24x24)
產品目錄頁面: 1080 (CN2011-ZH PDF)
其它名稱: 576-3537
Micrel, Inc.
KSZ8692MPB/KSZ8692XPB
March 2010
28
M9999-031810-4.0
Pin Number
Pin Name
Pin Type
Pin Description
E18
UART 2 CTSN
/GPIO[6]
I/O
UART 2 CTS or general purpose I/O Pin[6]
Pin Number
Pin Name
Pin Type
Pin Description
U20, U19
TOUT[1:0]/
GPIO[5:4]
I/O
Timer 1/0 out or General Purpose I/O Pin[5:4]
V20, T18,
V19, U18
EINT[3:0]/
GPIO[3:0]
I/O
External Interrupt Request or General Purpose I/O Pin[3:0]
I2S Interface
C20
SCKIN
I
External crystal or clock input for I2S clock
The maximum supported frequency is 49.2MHz
D20
SCKOUT
O
External crystal out for I2S clock
C19
I2S_MCLK
O
I2S master clock out
This clock is of same frequency as SCKIN
B20
I2S_BCLK
O
I2S bit clock out
B19
I2S_LRCLK
O
Left/right select
A19
I2S_SDO
O
Serial data out
A20
I2S_SDI
I
Serial data in
MDIO/MDC Interface
H18
MDC
Ipu/O
Clock for station management
H17
MDIO
Ipu/O
Serial data for station management
I2C/SPI Interface
E14
SPCK_SCL
Ipu/O
SPI mode: master clock Output
I2C mode: serial clock output
D17
SPMOSI_SDA
Ipu/O
SPI mode: master data out, slave data in
I2C mode: serial data
D16
SPMISO
I
SPI master data in, slave data out
D15
SPICS
Ipu/O
SPI chip select
F13
SPI_RDY
I
Micrel SPI mode ready signal
PCI Interface Signals
C3
PRSTN
I
PCI Reset, asserted Low
In Host Bridge Mode, the PCI Reset pin is an input. This pin as well as the
reset pin of all the devices on the PCI bus could be driven by WRSTO.
In Guest Bridge Mode, this pin is input. The system reset to drive this pin.
B2
PCLK
I
PCI Bus Clock input.
This signal provides the timing for the PCI bus transactions. This signal is used to
drive the PCI bus interface and the internal PCI logic. All PCI bus signals are
sampled on the rising edges of the PCLK. PCLK can operate from 20MHz to
33MHz, or 66MHz.
E4
GNT3N
O
PCI Bus Grant 3
Assert Low.
In Host Bridge Mode, this is an output signal from the internal PCI arbiter to
grant PCI bus access to the master driving REQ3N.
In Guest Bridge Mode, this is unused.
(No connect for KSZ8692XPB)
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