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參數(shù)資料
| 型號： | KSZ8692XPB |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 17/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM9 PHY 10/100MBPS 400-PBGA |
| 標準包裝： | 40 |
| 系列： | KSZx692 |
| 應用： | 網(wǎng)絡和通信 |
| 核心處理器： | ARM9 |
| 程序存儲器類型： | 外部程序存儲器 |
| 控制器系列： | KSZ |
| 接口： | EBI/EMI，以太網(wǎng)，I²C，I²S，PCI，SPI，UART/USART，USB |
| 輸入/輸出數(shù)： | 20 |
| 電源電壓： | 1.235 V ~ 1.365 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BGA |
| 包裝： | 托盤 |
| 供應商設備封裝： | 400-PBGA（24x24） |
| 產(chǎn)品目錄頁面： | 1080 (CN2011-ZH PDF) |
| 其它名稱： | 576-3537 |
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Micrel, Inc.
KSZ8692MPB/KSZ8692XPB
March 2010
24
M9999-031810-4.0
Pin Number
Pin Name
Pin Type
Pin Description
T2, U1, L5,
N4, P3, R2,
T1, M4, K5,
N3, P2, R1,
L4, M3, P1,
K4
SDATA[15..0]
Ipu/O
SRAM DATA Bus.
Bidirectional Bus for 16-bit DATA In and DATA Out. The
KSZ8692MPB/KSZ8692XPB also supports 8-bit data bus for
ROM/SRAM/FLASH/EXTIO cycles.
This data bus is shared between NAND, ROM/SRAM/FLASH/EXTIO devices.
L3
ECS2
O
External I/O Chip Select 2, asserted Low.
Three External I/O banks are provided for external memory-mapped I/O
operations. Each I/O bank stores up to 16Kbytes. ECSN signals indicate
which of the three I/O banks is selected.
N1
ECS1
O
External I/O Chip Select 1, asserted Low.
Three External I/O banks are provided for external memory-mapped I/O
operations. Each I/O bank stores up to 16Kbytes. ECSN signals indicate
which of the three I/O banks is selected.
M2
ECS0
O
External I/O Chip Select 0, asserted Low.
Three External I/O banks are provided for external memory-mapped I/O
operations. Each I/O bank stores up to 16Kbytes. ECSN signals indicate
which of the three I/O banks is selected.
K3
RCSN1
O
ROM/SRAM/FLASH(NOR) Chip select 1, asserted Low.
The KSZ8692MPB/KSZ8692XPB can access up to two external
ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to
map the CPU addresses into physical memory banks.
L1
RCSN0
O
ROM/SRAM/FLASH(NOR) Chip select 0, asserted Low.
The KSZ8692MPB/KSZ8692XPB can access up to two external
ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to
map the CPU addresses into physical memory banks.
This bank is configurable as boot option
N2
EWAITN
I
External Wait asserted Low.
This signal is asserted when an external I/O device or
ROM/SRAM/FLASH(NOR) bank needs more access cycles than those
defined in the corresponding control register.
M1
EROEN
(WRSTPLS)
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Output Enable, asserted Low.
When asserted, this signal controls the output enable port of the specified
ROM/SRAM/FLASH memory and EXTIO device.
J5
ERWEN1
O
ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted Low.
When asserted, this signal controls the byte write enable of the memory
device SDATA[15..8] for ROM/SRAM/FLASH and EXTIO access.
J4
ERWEN0
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted Low.
When asserted, this signal controls the byte write enable of the memory
device SDATA[7..0 or 15..0] for ROM/SRAM/FLASH and EXTIO access.
R3
NCLE
Ipd/O
NAND command Latch Enable
NCLE controls the activating path for command sent to NAND flash.
U2
NALE
Ipd/O
NAND Address Latch Enable
NALE controls the activating path for address sent to NAND flash.
T3
NCEN1
O
NAND Bank Chip Enable 1, asserted low
NAND device bank 1 selection control.
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