參數(shù)資料
型號(hào)： KSZ8692XPB
廠商： Micrel Inc
文件頁數(shù)： 29/42頁
文件大小： 0K
描述： IC ARM9 PHY 10/100MBPS 400-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： KSZx692
應(yīng)用： 網(wǎng)絡(luò)和通信
核心處理器： ARM9
程序存儲(chǔ)器類型： 外部程序存儲(chǔ)器
控制器系列： KSZ
接口： EBI/EMI，以太網(wǎng)，I²C，I²S，PCI，SPI，UART/USART，USB
輸入/輸出數(shù)： 20
電源電壓： 1.235 V ~ 1.365 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 400-BGA
包裝： 托盤
供應(yīng)商設(shè)備封裝： 400-PBGA（24x24）
產(chǎn)品目錄頁面： 1080 (CN2011-ZH PDF)
其它名稱： 576-3537
Micrel, Inc.
KSZ8692MPB/KSZ8692XPB
March 2010
35
M9999-031810-4.0
Pin Number
Pin Name
Pin Type
Pin Description
M1
EROEN
(WRSTPLS)
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Output Enable, asserted Low.
When asserted, this signal controls the output enable port of the specified
ROM/SRAM/FLASH memory and EXTIO device.
During reset, this pin is used for Watchdog Timer Reset Polarity Select.
This is a power strapping option pin for watchdog reset output polarity.
“0” = WRSTO is selected as active high (default)
“1” = WRSTO is selected as active low.
This pin is shared with the EROEN pin.
J4
ERWEN0
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted Low.
When asserted, these signals control the byte write enable of the memory device
for ROM/SRAM/FLASH and EXTIO access.
During ARM tic test mode, this pin is TESTACK.
During reset, this pin is the input strap option to enable MII mode at port0 (WAN
port)
0: MII mode (default)
1: Factory Reserved
R3
NCLE
Ipd/O
NAND command Latch Enable
NCLE controls the activating path for command sent to NAND flash.
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [2]. This bit along with configuration register bits [1:0] is used
for boot program. This pin, along with NALE and NWEN, is used to specify NAND
Flash size.
[NCLE, NALE, NWEN]
000 = 64Mbit
001 = 128Mbit (default)
010 = 256Mbit
011 = 512Mbit
100 = 1Gbit
101 = 2Gbit
110 = 4Gbit
111 = 8Gbit
U2
NALE
Ipd/O
NAND Address Latch Enable
NALE controls the activating path for address sent to NAND flash.
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [1]. This bit along with configuration register bits [2], [0] is
used for boot program. This pin, along with NCLE and NWEN, is used to specify
NAND Flash size.
[NCLE, NALE, NWEN]
000 = 64Mbit
001 = 128Mbit (default)
010 = 256Mbit
011 = 512Mbit
100 = 1Gbit
101 = 2Gbit
110 = 4Gbit
111 = 8Gbit
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