參數(shù)資料
型號(hào): KSZ8692XPB
廠商: Micrel Inc
文件頁數(shù): 28/42頁
文件大?。?/td> 0K
描述: IC ARM9 PHY 10/100MBPS 400-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: KSZx692
應(yīng)用: 網(wǎng)絡(luò)和通信
核心處理器: ARM9
程序存儲(chǔ)器類型: 外部程序存儲(chǔ)器
控制器系列: KSZ
接口: EBI/EMI,以太網(wǎng),I²C,I²S,PCI,SPI,UART/USART,USB
輸入/輸出數(shù): 20
電源電壓: 1.235 V ~ 1.365 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 400-BGA
包裝: 托盤
供應(yīng)商設(shè)備封裝: 400-PBGA(24x24)
產(chǎn)品目錄頁面: 1080 (CN2011-ZH PDF)
其它名稱: 576-3537
Micrel, Inc.
KSZ8692MPB/KSZ8692XPB
March 2010
34
M9999-031810-4.0
Power-up Strapping Options
Certain pins are sampled upon power up or reset to initialize KSZ8692MPB/KSZ8692XPB system registers per system
configuration requirements.
Pin Number
Pin Name
Pin Type
Pin Description
E3
SADDR[0]
Ipd/O
During reset, this pin is the input strap option for NAND Boot small page size
0 = 512 Bytes (default)
1 = 528 Bytes
E1, E2
SADDR[2:1]
Ipd/O
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [7:6]. These pins are used to specify number of active banks
(CE#) in cascade.
00 = 1 bank (default)
01 = 2 banks
F4
SADDR[3]
Ipd/O
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [8], NAND Flash type. This pin is used to specify using large
or small block NAND Flash as a boot bank as follows:
“0” = small block (default)
“1” = large block
F5
SADDR[4]
Ipd/O
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [4], NAND Flash type. This pin is used to specify number of
NAND Flash in parallel for combined data width as follows:
“0” = 1 NAND Flash (default)
“1” = 2 NAND Flash
F3
SADDR[5]
Ipu/O
During reset, this pin is the input strap option to enter ARM9 tic test mode
0: ARM tic test mode (factory reserved)
1: Normal mode (default)
F2
SADDR[6]
Ipd/O
During reset, this pin is the input strap option for NAND FLASH device support
automatic page crossing
0: NAND FLASH device does not support automatic page crossing (default)
1: NAND FLASH device supports automatic page crossing
G1
SADDR[7]
Ipd/O
During reset, this pin is a strapping option for B0SIZE, Bank 0 Data Access Size.
This is applicable to ROM/SRAM/FLASH and NAND boot bank.
Bank 0 is used for boot program. This pin is used to specify the size of the bank 0
data bus width as follow:
“0” = one byte (default)
“1” = half word
F1
SADDR[8]
Ipd/O
During reset, this pin is the a strapping option for BTSEL:
“0” = Boot select from NOR flash (default)
“1” = Boot select from NAND flash
G2
SADDR[9]
Ipd/O
During reset, this pin is the a strapping option for BYP_SYSPLL:
“0” = Use systems PLL (default)
“1” = Bypass systems PLL, use external clock (factory reserved)
G4
SADDR[10]
Ipd/O
During reset, this pin is a strapping option for BYP_CLKSEL:
“0” = Select 200MHz external clock (default)
“1” = Select 250MHz external clock (factory reserved)
G3
SADDR[11]
Ipd/O
During reset, this pin is the input strap option to enable MII mode at port1 (LAN
port)
0: MII mode (default)
1: Factory Reserved
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