參數(shù)資料
型號: KSZ8692XPB
廠商: Micrel Inc
文件頁數(shù): 25/42頁
文件大?。?/td> 0K
描述: IC ARM9 PHY 10/100MBPS 400-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: KSZx692
應(yīng)用: 網(wǎng)絡(luò)和通信
核心處理器: ARM9
程序存儲器類型: 外部程序存儲器
控制器系列: KSZ
接口: EBI/EMI,以太網(wǎng),I²C,I²S,PCI,SPI,UART/USART,USB
輸入/輸出數(shù): 20
電源電壓: 1.235 V ~ 1.365 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 400-BGA
包裝: 托盤
供應(yīng)商設(shè)備封裝: 400-PBGA(24x24)
產(chǎn)品目錄頁面: 1080 (CN2011-ZH PDF)
其它名稱: 576-3537
Micrel, Inc.
KSZ8692MPB/KSZ8692XPB
March 2010
31
M9999-031810-4.0
Pin Number
Pin Name
Pin Type
Pin Description
A10
PERRN
I/O
PCI Parity Error signal, asserted Low.
The KSZ8692MPB/KSZ8692XPB asserts PERRN when it checks and detects
a bus parity error. When it generates the PAR output, the
KSZ8692MPB/KSZ8692XPB monitors for any reported parity error on
PERRN.
When the KSZ8692MPB/KSZ8692XPB is the bus master and a parity error is
detected, the KSZ8692MPB/KSZ8692XPB sets error bits on the control status
registers. It completes the current data burst transaction, then stop the
operation. After the Host clears the system error, the
KSZ8692MPB/KSZ8692XPB continues its operation.
C9
SERRN
O
(open drain)
PCI System Error signal, asserted Low.
If an address parity error is detected, the KSZ8692MPB/KSZ8692XPB asserts
the SERRN signal two clocks after the failing address.
C4
M66EN
I
PCI 66MHz Enable
When asserted, this signal indicates the PCI Bus segment is operating at
66MHz.
This pin is mainly used in Guest bridge mode when the PCLK is driven by the
Host bridge.
F6
PCLKOUT3
O
PCI Clock output 3
(No connect for KSZ8692XPB)
D1
PCLKOUT2
O
PCI Clock output 2
(No connect for KSZ8692XPB)
D2
PCLKOUT1
O
PCI Clock output 1
E5
PCLKOUT0
O
PCI Clock output 0.
This signal provides the timing for the PCI bus transactions. This signal is
used to drive the PCI bus interface and the internal PCI logic. All PCI bus
signals are sampled on the rising edges of the PCLK. PCLK can operate from
20MHz to 33MHz, or 66MHz.
In Host Bridge Mode, this is an output signal for all the devices on the PCI bus
to sample data and control signals. Connect this clock to drive PCLK input.
In Guest Bridge Mode, this is not used.
A8
CLKRUNN
I/O
This is a CardBus only signal. The CLKRUNN signal is used by portable
CardBus devices to request the system to turn on the bus clock. Output is not
generated.
C2
MPCIACTN
I/O
Mini-PCI active. This signal is asserted by the PCI device to indicate that its
current function requires full system performance. MPCIACTN is an open
drain output signal.
D5
PBMS
I
PCI Bridge Mode Select
Select the operating mode of the PCI Bridge.
When PBMS is High, the Host Bridge Mode is selected and on chip PCI bus
arbiter is enabled.
When PBMS is Low, the Guest Bridge Mode is selected and the on-chip
arbiter is disabled.
A1
PMEN
O (open
drain)
PCI Power Management Enable (active low)
This pin is to inform the external PCI host that KSZ8692MPB/KSZ8692XPB
has detected a wake-up event.
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