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參數(shù)資料
| 型號(hào)： | LH28F320S3H-L |
| 廠商： | Sharp Corporation |
| 英文描述： | 32 M-bit(4 MB x 8/2 MB x 16)Smart3 Flash Memories(32M位 (4M位 x 8/2M位 x 16) Smart3 技術(shù)閃速存儲(chǔ)器) |
| 中文描述： | 32 M位（4字節(jié)× 8 / 2 MB的× 16）Smart3閃存（32兆位（4分位x 8/2M位× 16）Smart3技術(shù)閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 12/51頁 |
| 文件大?。?/td> | 340K |
| 代理商： | LH28F320S3H-L |
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on the rising edge of WE# or CE# (whichever
goes high first).
ID = Data read from identifier codes.
QD = Data read from query database.
Following the Read Identifier Codes command, read
operations access manufacture, device and block status
codes. See
Section 4.2
for read identifier code data.
LH28F320S3-L/S3H-L
- 12 -
COMMAND
BUS CYCLES
REQ
’
D.
1
≥
2
≥
2
2
2
2
2
NOTE
FIRST BUS CYCLE
Oper
(NOTE 1)
Addr
(NOTE 2)
Data
(NOTE 3)
Oper
(NOTE 1)
Addr
(NOTE 2)
Data
(NOTE 3)
Write
X
FFH
Write
X
90H
Write
X
98H
Write
X
70H
Write
BA
20H
Write
X
30H
Write
WA
40H
SECOND BUS CYCLE
Read Array/Reset
Read Identifier Codes
Query
Read Status Register
Clear Status Register
Block Erase Setup/Confirm
Full Chip Erase Setup/Confirm
Word/Byte Write Setup/Write
Alternate Word/Byte Write
Setup/Write
Multi Word/Byte Write
Setup/Confirm
Block Erase and (Multi)
Word/Byte Write Suspend
Confirm and Block Erase and
(Multi) Word/Byte Write Resume
Block Lock-Bit Set
Setup/Confirm
Block Lock-Bit Reset
Setup/Confirm
STS Configuration
Level-Mode for Erase
and Write (RY/BY# Mode)
STS Configuration
Pulse-Mode for Erase
STS Configuration
Pulse-Mode for Write
STS Configuration Pulse-Mode
for Erase and Write
NOTES :
1.
B
US
operations are defined in
Table 2.1
and
Table 2.2
.
2.
X = Any valid address within the device.
IA = Identifier code address : see
Fig. 2
.
QA = Query offset address.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
3.
SRD = Data read from status register. See
Table 13.1
for a description of the status register bits.
WD = Data to be written at location WA. Data is latched
4
Read
Read
Read
IA
QA
X
ID
QD
SRD
5
Write
Write
Write
BA
X
WA
D0H
D0H
WD
5, 6
2
5, 6
Write
WA
10H
Write
WA
WD
≥
4
9
Write
WA
E8H
Write
WA
N
–
1
1
5
Write
X
B0H
1
5
Write
X
D0H
2
7
Write
BA
60H
Write
BA
01H
2
8
Write
X
60H
Write
X
D0H
2
Write
X
B8H
Write
X
00H
2
Write
X
B8H
Write
X
01H
2
Write
X
B8H
Write
X
02H
2
Write
X
B8H
Write
X
03H
Table 3 Command Definitions
(NOTE 10)
4.
5.
If the block is locked, WP# must be at V
IH
to enable
block erase or (multi) word/byte write operations.
Attempts to issue a block erase or (multi) word/byte write
to a locked block while RP# is V
IH
.
Either 40H or 10H is recognized by the WSM as the
byte write setup.
A block lock-bit can be set while WP# is V
IH
.
WP# must be at V
IH
to clear block lock-bits. The clear
block lock-bits operation simultaneously clears all block
lock-bits.
Following the Third Bus Cycle, inputs the write address
and write data of "N" times. Finally, input the confirm
command "D0H".
10. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
6.
7.
8.
9.
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