參數(shù)資料
型號(hào)： LH28F320S3H-L
廠商： Sharp Corporation
英文描述： 32 M-bit(4 MB x 8/2 MB x 16)Smart3 Flash Memories(32M位 (4M位 x 8/2M位 x 16) Smart3 技術(shù)閃速存儲(chǔ)器)
中文描述： 32 M位（4字節(jié)× 8 / 2 MB的× 16）Smart3閃存（32兆位（4分位x 8/2M位× 16）Smart3技術(shù)閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 13/51頁(yè)
文件大?。?/td> 340K
代理商： LH28F320S3H-L
- 13 -
Block is Unlocked
DQ
0
= 0
Block is Locked
DQ
0
= 1
Last erase operation
DQ
1
= 0
completed successfully
Last erase operation did
DQ
1
= 1
not completed successfully
Reserved for Future Use
DQ
2-7
LH28F320S3-L/S3H-L
4.1
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, full chip erase, (multi) word/byte write
or block lock-bit configuration, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend and (Multi)
Word/Byte Write Suspend command. The Read
Array command functions independently of the V
PP
voltage and RP# must be V
IH
.
Read Array Command
4.2
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in
Fig. 2
retrieve the manufacture, device, block
lock configuration and block erase status (see
Table 4
for identifier code values). To terminate the
operation, write another valid command. Like the
Read Array command, the Read Identifier Codes
command functions independently of the V
PP
voltage and RP# must be V
IH
. Following the Read
Identifier Codes command, the following information
can be read :
Read Identifier Codes Command
Table 4 Identifier Codes
CODE
NOTE :
1.
X selects the specific block status code to be read. See
Fig. 2
for the device identifier code memory map.
4.3
The status register may be read to determine when
a block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration is complete and
whether the operation completed successfully (see
Table 13.1
). It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE# (Either CE
0
# or CE
1
#) , whichever occurs.
OE# or CE# (Either CE
0
# or CE
1
#) must toggle to
V
IH
before further reads to update the status
register latch. The Read Status Register command
functions independently of the V
PP
voltage. RP#
must be V
IH
.
Read Status Register Command
The extended status register may be read to
determine multi byte write availability (see
Table
13.2
). The extended status register may be read at
any time by writing the Multi Byte Write command.
After writing this command, all subsequent read
operations output data from the extended status
register, until another valid command is written. The
contents of the extended status register are latched
on the falling edge of OE# or CE# (Either CE
0
# or
CE
1
#) , whichever occurs last in the read cycle.
Multi Byte Write command must be re-issued to
update the extended status register latch.
4.4
Status register bits SR.5, SR.4, SR.3 and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see
Table 13.1
).
By allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
Clear Status Register Command
ADDRESS
000000H
000001H
000002H
000003H
X0004H
(NOTE 1)
X0005H
(NOTE 1)
DATA
Manufacture Code
B0
Device Code
D4
Block Status Code
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