參數(shù)資料
型號(hào): LH28F320S3H-L
廠商: Sharp Corporation
英文描述: 32 M-bit(4 MB x 8/2 MB x 16)Smart3 Flash Memories(32M位 (4M位 x 8/2M位 x 16) Smart3 技術(shù)閃速存儲(chǔ)器)
中文描述: 32 M位(4字節(jié)× 8 / 2 MB的× 16)Smart3閃存(32兆位(4分位x 8/2M位× 16)Smart3技術(shù)閃速存儲(chǔ)器)
文件頁數(shù): 46/51頁
文件大?。?/td> 340K
代理商: LH28F320S3H-L
NOTES :
1.
These specifications are valid for all product versions
(packages and speeds).
2.
If RP# is asserted while a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
operation is not executing, the reset will complete within
100 ns.
LH28F320S3-L/S3H-L
- 46 -
6.2.7 RESET OPERATIONS
RP# (P)
V
IL
(A) Reset During Read Array Mode
(B) Reset During Block Erase, Full Chip Erase, (Multi) Word/Byte Write
or Block Lock-Bit Configuration
V
IH
High Z
V
IH
High Z
V
OL
V
IL
V
OL
STS (R)
STS (R)
RP# (P)
V
IL
V
IH
RP# (P)
V
IL
V
CC
2.7 V/3.3 V
(C) V
CC
Power Up Timing
t
PLPH
t
PLRH
t
PLPH
t
23VPH
Fig. 19 AC Waveform for Reset Operation
Reset AC Specifications
(NOTE 1)
3.
A reset time, t
PHQV
, is required from the latter of STS
going High Z or RP# going high until outputs are valid.
When the device power-up, holding RP#-low minimum
100 ns is required after V
CC
has been in predefined
range and also has been in stable there.
4.
V
CC
= 2.7 to 3.6 V
MIN.
V
CC
= 3.3±0.3 V
MIN.
UNIT
SYMBOL
PARAMETER
NOTE
MAX.
MAX.
t
PLPH
RP# Pulse Low Time (If RP# is tied to V
CC
,
this specification is not applicable)
RP# Low to Reset during Block Erase,
Full Chip Erase, (Multi) Word/Byte Write
or Block Lock-Bit Configuration
V
CC
2.7 V to RP# High
V
CC
3.0 V to RP# High
100
100
ns
t
PLRH
2, 3
21.5
21.1
μs
t
23VPH
4
100
100
ns
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