xv
List of Figures
LH77790B Block Diagram..............................................................................................1-4
ARM7DI Core Block Diagram ........................................................................................3-2
Cache Organization in Cache Mode ..............................................................................4-3
Cache Mapping in SRAM Mode.....................................................................................4-4
Memory and Peripheral Interface Block Diagram ..........................................................5-2
Logical to Physical Address Mapping ............................................................................5-6
ECE Example...............................................................................................................5-12
Byte Read from x8 SRAM............................................................................................5-23
Byte Write to x8 SRAM ................................................................................................5-24
Byte Write to x8 SRAM with External WAIT Cycles.....................................................5-25
Word Read to x16 SRAM.............................................................................................5-26
Word Write to x16 SRAM.............................................................................................5-27
Byte Read from x8 DRAM............................................................................................5-28
Byte Write to x8 DRAM ................................................................................................5-29
Word Read from x16 DRAM Page Mode (FCAS = 010, BCAS = 01)..........................5-30
Word Write to x16 DRAM Page Mode (FCAS = 010, BCAS = 01) ..............................5-31
Word Write to x8 DRAM Page Mode (FCAS = 010, BCAS = 01)
DRAM Page Boundary Crossing..............................................................................5-32
DRAM CAS Before RAS Refresh Cycle.......................................................................5-33
Clock and Power Management Unit Block Diagram ......................................................6-2
External Clock Circuitry Example...................................................................................6-4
UART0 Block Diagram...................................................................................................7-2
SIR Interface Example ...................................................................................................8-1
SIR Block Diagram.........................................................................................................8-2
IrDA Mode......................................................................................................................8-3
DASK Mode: Modulator .................................................................................................8-5
Dask Mode: Demodulator ..............................................................................................8-6
PWM Timing Diagram....................................................................................................9-1
Functional Block Diagram ..............................................................................................9-3
PWM0 Running in Normal Mode....................................................................................9-5
PWM0, PWM1, PWM2 Running in Synchronous Mode.................................................9-7
PWMn_INV Example ...................................................................................................9-12
Block Diagram..............................................................................................................10-2
Single Scan Mode 4-Bit Transfer .................................................................................10-3
Single Scan Mode 8-Bit Transfer .................................................................................10-3
Dual Scan Mode (Always 4-Bit Transfer).....................................................................10-4
CP1 Clock Pulse High Time.......................................................................................10-12
LCD Panel in Dual Mode............................................................................................10-14
LCD Panel in Division Mode ......................................................................................10-17
LCD Panel Before Scrolling .......................................................................................10-19
LCD Panel After Scrolling ..........................................................................................10-19
Format 0 Gray Shade Logic.......................................................................................10-21
Format 1 Gray Shade Logic.......................................................................................10-21
MCLK and CP1 Relationship .....................................................................................10-24
MCLK and CP1 Relationship .....................................................................................10-31