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Table of Contents
Chapter 1 Overview
Introduction.................................................................................................................1-1
Features.....................................................................................................................1-2
Development Environment.........................................................................................1-3
Block Diagram............................................................................................................1-4
Convention.................................................................................................................1-4
Accessing Registers...................................................................................................1-4
Chapter 2 Pin Descriptions
Chapter 3 ARM7DI Core
Introduction.................................................................................................................3-1
Features.....................................................................................................................3-1
Block Diagram............................................................................................................3-2
Chapter 4 On-chip Memory
Introduction.................................................................................................................4-1
Cache.........................................................................................................................4-1
Features .................................................................................................................4-1
Register Map..........................................................................................................4-1
General Operation..................................................................................................4-2
Register Description...............................................................................................4-2
Cache Mode...........................................................................................................4-3
SRAM Mode...........................................................................................................4-4
Flush Mode.............................................................................................................4-5
Invalidate Mode......................................................................................................4-5
Local SRAM ...............................................................................................................4-6
Features .................................................................................................................4-6
Register Map..........................................................................................................4-6
General Operation..................................................................................................4-6
Register Description...............................................................................................4-7
Chapter 5 Memory & Peripheral Interface
Introduction.................................................................................................................5-1
Features.....................................................................................................................5-1
Block Diagram............................................................................................................5-2
Register Map..............................................................................................................5-3
Upon Reset ................................................................................................................5-4
General Operation......................................................................................................5-5
Memory Management ................................................................................................5-5
Logical to Physical Mapping...................................................................................5-6
Memory Segments .................................................................................................5-7
Memory Banks .......................................................................................................5-7