LH77790B User’s Guide
List of Tables
xviii
MSR Fields...................................................................................................................7-12
BAUD Generation ........................................................................................................7-13
Baud Rate Division.......................................................................................................7-14
SIR External Interface....................................................................................................8-2
SIR Register Offset ........................................................................................................8-2
SIR_CTLR Fields ...........................................................................................................8-7
PWM Frequency Range.................................................................................................9-1
PWM External Interface .................................................................................................9-3
PWM Register Map........................................................................................................9-4
Synchronous Mode ........................................................................................................9-6
PWMn_DIV Fields..........................................................................................................9-9
PWMn_DIV Update........................................................................................................9-9
PWMn_TC Update.......................................................................................................9-10
PWMn_DC Update.......................................................................................................9-11
PWMn_INV Fields........................................................................................................9-12
PWMn_INV Update......................................................................................................9-12
PWMn_ENB Fields ......................................................................................................9-13
PWMn_SYNC Fields....................................................................................................9-13
Static Programming Steps ...........................................................................................9-14
Dynamic Programming Steps ......................................................................................9-14
Synchronous Mode Programming Steps .....................................................................9-15
Synchronous Mode Programming Steps .....................................................................9-16
LCD Panel Interface Signals........................................................................................10-2
LCD Display Data.........................................................................................................10-3
LCD Controller Register Map.......................................................................................10-5
LCD_MODE, DISP Bit..................................................................................................10-6
LCD_MODE, REV Bit...................................................................................................10-6
LCD_MODE, SCAN Bit................................................................................................10-6
LCD_MODE, OR Bit.....................................................................................................10-7
LCD_MODE, GRAY Bit................................................................................................10-7
LCD_MODE, XSIZE.....................................................................................................10-7
Transfer Size................................................................................................................10-8
LCD_MODE, LCDC .....................................................................................................10-8
LCD_MODE, LCDA......................................................................................................10-8
LCD_MODE Register Summary ..................................................................................10-9
LCD Controller Display Modes.....................................................................................10-9
Relation Between LCD_BC and the Number of Display Pixels..................................10-10
Padded Frame Buffer Example..................................................................................10-11
Line Pulse Width ........................................................................................................10-12
Relation Between (LCD_DUTY) and Number of CP1 Pulses Per Frame..................10-13
Relationship between Screen #1 and Display Modes................................................10-15
Relationship Between Screen #2 and Display Modes ...............................................10-16
Relationship Between (LCD_VLC1) and Screen No. 1 Lines ....................................10-17
Relationship Between LCD_VDLT and Address Difference ......................................10-18
Relationship between Frame Buffer Byte, (x, y) Pair and LCD Bit Format ................10-20
Four Gray Shades......................................................................................................10-20
Example of Pixel 1 State in Gray Scale Mode ...........................................................10-22