參數(shù)資料
型號: M12S64322A-6TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 512K x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝: 0.400 X 0.875 INCH, 0.50 MM PITCH, LEAD FREE, TSOP2-86
文件頁數(shù): 16/46頁
文件大?。?/td> 746K
代理商: M12S64322A-6TG
ES MT
M12S64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision
:
1.0
16/46
Write command
(CS ,CAS ,
WE
= Low, RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
Read command
(CS , CAS = Low, RAS ,
WE
= High)
Read data is available afterCAS latency requirements have been met.
This command sets the burst start address given by the column address.
CBR (auto) refresh command
(CS , RAS , CAS = Low,
WE
, CKE = High)
This command is a request to begin the CBR refresh operation. The refresh
address is generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a
row activate command.
During t
RC
period (from refresh command to refresh or activate command), the
DRAM cannot accept any other command.
CLK
CLK
CKE
CKE
CS
RAS
WE
BA0, BA1
(Bank select)
BA0, BA1
(Bank select)
A10
A10
Add
Add
CAS
H
H
Col.
Fig. 4 Column address and
write command
Fig. 5 Column address and
read command
CLK
CKE
BA0, BA1
(Bank select)
A10
Add
H
Fig. 6 Auto refresh command
Col.
CS
RAS
WE
CAS
CS
RAS
WE
CAS
相關(guān)PDF資料
PDF描述
M12S64322A-7BG 512K x 32 Bit x 4 Banks Synchronous DRAM
M12S64322A-7TG 512K x 32 Bit x 4 Banks Synchronous DRAM
M13S128168A 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S128168A-5BG 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S128168A-5T 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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