參數(shù)資料
型號: M12S64322A-6TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 512K x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝: 0.400 X 0.875 INCH, 0.50 MM PITCH, LEAD FREE, TSOP2-86
文件頁數(shù): 17/46頁
文件大?。?/td> 746K
代理商: M12S64322A-6TG
ES MT
M12S64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision
:
1.0
17/46
Self refresh entry command
(CS ,RAS ,CAS , CKE = Low ,
WE
= High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the DRAM exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Burst stop command
(CS ,
WE
= Low,RAS ,CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
No operation
(CS = Low ,RAS ,CAS ,
WE
= High)
This command is not a execution command. No operations begin or terminate by
this command.
CLK
CKE
CS
RAS
WE
BA0, BA1
(Bank select)
A10
Add
CAS
CLK
CKE
(Bank select)
A10
Add
H
Fig. 7 Self refresh entry
command
Fig. 8 Burst stop command
CLK
CKE
BA0, BA1
(Bank select)
A10
Add
H
Fig. 9 No operation
CS
RAS
WE
CAS
CS
RAS
WE
CAS
相關PDF資料
PDF描述
M12S64322A-7BG 512K x 32 Bit x 4 Banks Synchronous DRAM
M12S64322A-7TG 512K x 32 Bit x 4 Banks Synchronous DRAM
M13S128168A 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S128168A-5BG 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S128168A-5T 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
相關代理商/技術(shù)參數(shù)
參數(shù)描述
M12S64322A-7BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM
M12S64322A-7TG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM
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