參數(shù)資料
型號: M30240S9-XXXFP
廠商: Mitsubishi Electric Corporation
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: 單片16位CMOS微機(jī)
文件頁數(shù): 11/142頁
文件大小: 1637K
代理商: M30240S9-XXXFP
1-11
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Central Processing Unit (CPU)
2.0 Operation of Functional Blocks
The M30240 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data, and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as USB, timers, serial I/O, DMAC, CRC calculation circuit, A-D
converter, and I/O ports.
The following explains each unit.
2.1 Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.5. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
Figure 1.5:
Central processing unit register
2.1.1 Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer
and arithmetic/logic operations.
AAAAAAA
AAAAAAA
H
L
R0
(Note)
AAAAAAA
AAAAAAA
H
L
b15
b8 b7
b0
R1
(Note)
R2
(Note)
AAAAAAA
b15
b0
R3
(Note)
AAAAAAA
AAAAAAA
b15
b0
A0
(Note)
AAAAAAA
AAAAAAA
b15
b0
A1
(Note)
AAAAAAA
b15
b0
FB
(Note)
AAAAAAA
AAAAAAA
Data
registers
Address
registers
Frame base
registers
b15
b0
b15
b0
b15
b0
b15
b0
b0
b19
b0
b19
H
L
Program counter
Interrupt table
register
User stack pointer
Interrupt stack
pointer
Static base
register
Flag register
PC
INTB
USP
ISP
SB
FLG
Note: These registers consist of two register banks.
AAAAAAAAAAAAA
AAAAAAAAAAAAA
IPL
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