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參數(shù)資料
| 型號： | M30240S9-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 單片16位CMOS微機 |
| 文件頁數(shù)： | 57/142頁 |
| 文件大?。?/td> | 1637K |
| 代理商： | M30240S9-XXXFP |
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Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Universal Serial Bus
2.18.4.12 Endpoint 0 CSR (Control and Status Register)
The Endpoint 0 CSR (Control and Status Register), shown in Figure 1.44 contains the control and status in-
formation of Endpoint 0.
EP0CSR0 (OUT_PKT_RDY):
The USB FCU sets this bit to a “1” after it receives a valid SETUP/OUT token from the host. The CPU clears this
bit after unloading the packet from the FIFO by writing a “1” to EP0CSR6. The CPU should not clear the
OUT_PKT_RDY bit before it finishes decoding the host request. When EP0CSR2 (SEND_STALL) needs to be
set (because the CPU decodes an invalid or unsupported request) a “1” should be written to EP0CSR6 and
EP0CSR2 at the same time using the same instruction.
EP0CSR1 (IN_PKT_RDY):
The CPU writes a “1” to this bit after it finishes writing a packet of data to the endpoint 0 FIFO. The USB FCU
clears this bit after the packet is successfully transmitted to the host, or the EP0CSR5 (SETUP_END) bit is
set.
EP0CSR2 (SEND_STALL):
The CPU writes a “1” to this bit when it decodes an invalid or unsupported standard device request from the
host. When the OUT-PKT_RDY bit is a “1” at the time the CPU wants to set the SEND_STALL bit to a “1”, the
CPU must also set SERVICED_OUT_PKT_RDY to a “1” to clear the OUT-PKT_RDY at the same time as set-
ting the SEND_STALL bit. The USB FCU returns a STALL handshake for all subsequent IN/OUT transactions
(during control transfer data or status stages) while this bit is set. The CPU writes a “0” to clear it after it re-
ceives a new SETUP packet. It is up to the firmware to decide what SETUP packet should lead the clearing
of the SEND_STALL bit.
EP0CSR3 (DATA_END):
The CPU writes a “1” to this bit when it writes (IN data phase) or reads (OUT data phase) the last packet of
data to or from the FIFO. The CPU sets this bit at the same time as it sets the last IN_PKT_RDY bit or sets
the last SERVICED_OUT_PKT_RDY bit.This bit indicates to the USB FCU that the specific amount of data in
the setup phase is transferred. The USB FCU advances to the status phase once this bit is set. When the
status phase completes, the USB FCU clears this bit. When this bit is set to a “1”, and the host requests or
sends more data, the USB FCU returns a STALL handshake and terminates the current control transfer.
EP0CSR4 (FORCE_STALL):
The USB FCU sets this bit to a “1” to report an error status when one of the following occur:
Host sends an IN token in the absence of a SETUP stage
Host sends a bad data toggle in the STATUS stage, (i.e. DATA0 is used)
Host sends a bad data toggle in the SETUP stage, (i.e. DATA1 is used)
Host request more data than specified in the SETUP state,
(i.e. IN token comes after DATA_END bit is set)
Host sends more data than specified in the SETUP state,
(i.e. OUT token comes after DATA_END bit is set)
Host sends larger data packet than MAXP size
All of the conditions stated (except bad data toggle in the SETUP stage) cause the device to send a STALL
handshake for the current IN/OUT transaction. For the bad data toggle in the SETUP state, the device sends
ACK for the SETUP stage and then sends STALL for the next IN/OUT transaction. A STALL handshake
caused by the above listed conditions lasts for one transaction and terminates the ongoing control transfer.
Any packet after the STALL handshake will be seen as the beginning of a new control transfer.
The CPU writes a “0” to clear the FORCE_STALL status bit.
EP0CSR5 (SETUP_END):
The USB FCU sets this bit to a “1” if a control transfer has ended before the specific length of data is trans-
ferred during the data phase (status phase starts before DATA_END bit is set) or a control transfer has ended
before a new SETUP has arrived and before successfully completing the status phase. The CPU clears this
bit by writing a “1” to IN0CSR7. Once the CPU detects the SETUP_END bit as set, it should stop accessing
the FIFO to service the previous setup transaction. If the SETUP_END is caused by the reception of the SET-
UP packet prior to the end of the current control transfer, the OUT_PKT_RDY bit is set once the reception of
the SETUP packet has completed (without errors). After the OUT_PKT_RDY bit is set, the new SETUP packet
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30240SA | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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| M30240SC | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240SC-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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