參數(shù)資料
型號(hào): M30240S9-XXXFP
廠商: Mitsubishi Electric Corporation
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: 單片16位CMOS微機(jī)
文件頁數(shù): 94/142頁
文件大小: 1637K
代理商: M30240S9-XXXFP
1-94
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
UART0 through UART2
Figure 1.83: Typical transmit/receive timings in clock synchronous serial I/O mode Polarity select
function
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Tc
T
CLK
Stopped pulsing because transfer enable bit = “0”
Data is set in UARTi transmit buffer register
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f
1
, f
8
, f
32
)
n: value set to BRGi
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
CTSi
The above timing applies to the following settings:
Internal clock is selected.
CTS function is selected.
CLK polarity select bit = “0”.
Transmit interrupt cause select bit = “0”.
Transmit interrupt
request bit (IR)
“0”
“1”
Stopped pulsing because CTS = “H”
1 / f
EXT
Dummy data is set in UARTi transmit buffer register
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
RxDi
Receive complete
flag (Rl)
RTSi
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
Receive enable
bit (RE)
“0”
“1”
Receive data is taken in
Transferred from UARTi transmit buffer register to UARTi transmit register
Read out from UARTi receive buffer register
The above timing applies to the following settings:
External clock is selected.
RTS function is selected.
CLK polarity select bit = “0”.
f
EXT
: frequency of external clock
Transferto UARTi receive buffer register
Receive interrupt
request bit (IR)
“0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
Shown in ( ) are bit symbols.
Transferred from UARTi transmit buffer register to UARTi transmit register
Meet the following conditions are met when the CLK
input before data reception = “H”
Transmit enable bit “1”
Receive enable bit “1”
Dummy data write to UARTi transmit buffer register
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
Cleared to “0” when interrupt request is accepted, or cleared by software
Example of receive timing (when external clock is selected)
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