參數(shù)資料
型號: M36DR432B
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product
中文描述: 32兆位的2Mb x16插槽,雙行,頁閃存和4兆位256K x16的SRAM,多個存儲產(chǎn)品
文件頁數(shù): 31/46頁
文件大小: 328K
代理商: M36DR432B
31/46
M36DR432A, M36DR432B
Table 29. Flash Program, Erase Times and Program, Erase Endurance Cycles
(T
A
= –40 to 85°C; V
DDF
= 1.65V to 2.2V, V
PPF
= V
DDF
unless otherwise specified)
Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or
erase should perform significantly better.
2. Excludes the time needed to execute the sequence for program instruction.
Table 30. Flash Data Polling and Toggle Bits AC Characteristics
(1)
(T
A
= –40 to 85 °C; V
DDF
= 1.65V to 2.2V)
Note: 1. All other timings are defined in Read AC Characteristics table.
Parameter
Min
Max
(1)
Typ
Typical after
100k W/E Cycles
Unit
Parameter Block (4 KWord) Erase (Preprogrammed)
2.5
0.15
0.4
s
Main Block (32 KWord) Erase (Preprogrammed)
10
1
3
s
Bank Erase (Preprogrammed, Bank A)
2
6
s
Bank Erase (Preprogrammed, Bank B)
10
30
s
Chip Program
(2)
20
25
s
Chip Program (DPG, V
PP
= 12V)
(2)
10
s
Word Program
200
10
10
μs
Program/Erase Cycles (per Block)
100,000
cycles
Symbol
Parameter
Flash
Unit
Min
Max
t
EHQ7V
Chip Enable High to DQ7 Valid (Program, EF Controlled)
10
200
μs
Chip Enable High to DQ7 Valid (Block Erase, EF Controlled)
1
10
s
t
EHQV
Chip Enable High to Output Valid (Program)
10
200
μs
Chip Enable High to Output Valid (Block Erase)
1
10
s
t
Q7VQV
Q7 Valid to Output Valid (Data Polling)
0
ns
t
WHQ7V
Write Enable High to DQ7 Valid (Program, WF Controlled)
10
200
μs
Write Enable High to DQ7 Valid (Block Erase, WF
Controlled)
1
10
s
t
WHQV
Write Enable High to Output Valid (Program)
10
200
μs
Write Enable High to Output Valid (Block Erase)
1
10
s
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