- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359056 > M36DR432DA85ZA6T (意法半導(dǎo)體) 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product PDF資料下載
參數(shù)資料
| 型號： | M36DR432DA85ZA6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| 中文描述： | 32兆位的2Mb x16插槽，雙行，頁閃存和4兆位256K x16的SRAM，多個存儲產(chǎn)品 |
| 文件頁數(shù)： | 14/52頁 |
| 文件大小： | 834K |
| 代理商： | M36DR432DA85ZA6T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
M36DR432AD, M36DR432BD
14/52
dles all timings and verifies the correct execution
of the Program and Erase commands. Two bus
write cycles are required to unlock the Command
Interface. They are followed by a setup or confirm
cycle. The increased number of write cycles is to
ensure maximum data security.
The Program/Erase Controller provides a Status
Register whose output may be read at any time to
monitor the progress or the result of the operation.
The Command Interface is reset to Read mode
when power is first applied or exiting from Reset.
Command sequences must be followed exactly.
Any invalid combination of commands will reset
the device to Read mode
Flash Read/Reset Command.
The Read/Reset
command returns the device to Read mode. One
Bus Write cycle is required to issue the Read/Re-
set command and return the device to Read mode.
Subsequent Read operations will read the ad-
dressed location and output the data. The write cy-
cle can be preceded by the unlock cycles but it is
not mandatory.
Flash Read CFI Query Command.
The
CFI Query command is used to read data from the
Common Flash Interface (CFI) and the Electronic
Signature (Manufacturer or the Device Code, see
Table 5). The Read CFI Query Command consists
of one Bus Write cycle. Once the command is is-
sued the device enters Read CFI mode. Subse-
quent Bus Read operations read the Common
Flash Interface or Electronic Signature. Once the
device has entered Read CFI mode, only the
Read/Reset command should be used and no oth-
er. Issuing the Read/Reset command returns the
device to Read mode.
See Appendix B, Common Flash Interface, Tables
33, 34, and 35 for details on the information con-
tained in the Common Flash Interface memory ar-
ea.
Auto Select Command.
The Auto Select com-
mand uses the two unlock cycles followed by one
write cycle to any bank address to setup the com-
mand. Subsequent reads at any address will out-
put the Block Protection status, Protection
Register and Protection Register Lock or the Con-
figuration Register status depending on the levels
of A0 and A1 (see Tables 6, 7 and 8). Once the
Auto Select command has been issued only the
Read/Reset command should be used and no oth-
er. Issuing the Read/Reset command returns the
device to Read mode.
Set Configuration Register Command.
The
Flash component contains a Configuration Regis-
ter, see Table 7, Configuration Register.
It is used to define the status of the Reset/Power-
Down functions. The value for the Configuration
Register is always presented on A0-A15, the other
Read
address bits are ignored. Address input A10 de-
fines the status of the Reset/Power-Down func-
tions. If it is set to ‘0’ the Reset function is enabled,
if it is set to ‘1’ the Power-Down function is en-
abled. At Power Up the Configuration Register bit
is set to ‘0’.
The Set Configuration Register command is used
to write a new value to the Configuration Register.
The command uses the two unlock cycles followed
by one write cycle to setup the command and a
further write cycle to write the data and confirm the
command.
Program Command.
The Program command
uses the two unlock cycles followed by a write cy-
cle to setup the command and a further write cycle
to latch the Address and Data and start the Pro-
gram Erase Controller. Read operations within the
same bank output the Status Register after pro-
gramming has started.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole bank from ’0’ to ’1’. If the Program
command is used to try to set a bit from ‘0’ to ‘1’
Status Register Error bit DQ5 will be set to ‘1’, only
if V
PPF
is in the range of 11.4V to 12.6V.
Double Word Program Command.
This feature
is offered to improve the programming throughput
by writing a page of two adjacent words in parallel.
The V
PPF
supply voltage is required to be from
11.4V to 12.6V for the Double Word Program com-
mand.
The command uses the two unlock cycles followed
by a write cycle to setup the command. A further
two cycles are required to latch the address and
data of the two Words and start the Program Erase
Controller.
The addresses must be the same except for the
A0. The Double Word Program command can be
executed in Bypass mode to skip the two unlock
cycles.
Note that the Double Word Program command
cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Double Word Program command is used to try to
set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5
will be set to ‘1’.
Quadruple Word Program Command.
The
Quadruple Word Program command improves the
programming throughput by writing a page of four
adjacent words in parallel. The four words must
differ only for the addresses A0 and A1. The V
PPF
supply voltage is required to be from 11.4V to
12.6V for the Quadruple Word Program com-
mand.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M36DR432DA10ZA6T | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| M36DR432CZA | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| M36DR432BD85ZA6T | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product |
| M36DR432BD | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product |
| M36DR432B120ZA6T | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36DR432DZA | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| M36DR432-ZAT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| M36DR864CB85ZA6 | 功能描述:閃存 64M (4Mx16) 85ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M36DR864CB85ZA6T | 功能描述:閃存 64M (4Mx16) 85ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M36JGK90X | 制造商:Panasonic Industrial Company 功能描述:CRT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。