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參數(shù)資料
| 型號： | M5M5Y5636TG-25 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（524288 - Word的36位）網絡的SRAM |
| 文件頁數(shù)： | 10/27頁 |
| 文件大小： | 212K |
| 代理商： | M5M5Y5636TG-25 |
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MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
10
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5636TG REV.0.0
It should be noted that deselection of the SRAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the SRAM via E1# does not deactivate the
Echo Clocks.
CLK
A
ADD
E1#
E2# Bank1
E2 Bank2
Q(A)
Q(C)
B
C
D
E
F
DQ
Bank1
CQ
Bank1
CQ Bank1
+ CQ Bank2
Q(B)
Q(D)
DQ
Bank2
CQ
Bank2
Echo Clock Control in Two Banks
Note9. E1# does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously
deselected by E2 or E3 being sampled false.
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