參數(shù)資料
型號(hào)： M5M5Y5636TG-25
廠商： Mitsubishi Electric Corporation
英文描述： 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
中文描述： 18874368位（524288 - Word的36位）網(wǎng)絡(luò)的SRAM
文件頁(yè)數(shù)： 9/27頁(yè)
文件大小： 212K
代理商： M5M5Y5636TG-25
MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
9
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5636TG REV.0.0
Echo Clock
The SRAM features Echo Clocks, CQ1,CQ2, CQ1#, and CQ2# that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CLK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. The SRAM
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1# and CQ2#).
It should be noted that deselection of the SRAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the SRAM via E1# does not deactivate the
Echo Clocks.
Programmable Enable
The SRAM features two user programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active low
or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at HIGH, E2
functions as an active high enable. If EP2 is held to LOW, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows for banks of depth expansion to be accomplished with no additional logic. By programming the
enable inputs of four SRAMs in binary sequence (00,01,10,11) and driving the enable inputs with two address inputs, four SRAMs can
be made to look like one larger SRAM to the system.
Bank Enable Truth Table
EP2
EP3
E2
E3
Bank0
Bank1
Bank2
Bank3
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
Active Low
Active Low
Active High
Active High
Active Low
Active High
Active Low
Active High
A
E3#
E2#
E1#
CK
W#
DQ
CQ
Bank0
A
0
~A
20
7E1#
CK
W#
DQa~DQd
A
0
~A
18
A
19
A
20
A
E3
E2#
E1#
CK
W#
DQ
CQ
Bank1
A
0
~A
18
A
19
A
20
A
E3#
E2
E1#
CK
W#
DQ
CQ
Bank2
A
0
~A
18
A
19
A
20
A
E3
E2
E1#
CK
W#
DQ
CQ
Bank3
A
0
~A
18
A
19
A
20
CQ
Example Four Bank Depth Schematic
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