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參數(shù)資料
| 型號(hào)： | M5M5Y5636TG-25 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（524288 - Word的36位）網(wǎng)絡(luò)的SRAM |
| 文件頁(yè)數(shù)： | 7/27頁(yè) |
| 文件大?。?/td> | 212K |
| 代理商： | M5M5Y5636TG-25 |
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MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
7
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5636TG REV.0.0
Special Function
Burst Cycles
The SRAM provides an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write
implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the
counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the
SRAM by driving the ADV pin low, into Load mode.
CLK
ADD
E1#
ADV
W#
BWx#
DQ
CQ
D(A+3)
Write A
Burst Write
A+1
A
D(A+2)
D(A+1)
D(A)
Burst Write
A+2
Burst Write
A+3
Burst Write
A
B
Write B
CLK
A
ADD
E1#
ADV
W#
BWx#
DQ
CQ
Q(A)
Q(A+1)
Q(A+2)
Q(A+3)
Read A
Burst Read
A+1
Burst Read
A+2
Burst Read
A+3
Read B
B
Burst Read
B+1
Burst Read
Burst Write
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